[backend]为图着色引入保底修复
This commit is contained in:
Lixuanwang
@@ -5,6 +5,7 @@ add_library(riscv64_backend_lib STATIC
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RISCv64ISel.cpp
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RISCv64ISel.cpp
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RISCv64LLIR.cpp
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RISCv64LLIR.cpp
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RISCv64RegAlloc.cpp
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RISCv64RegAlloc.cpp
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RISCv64LinearScan.cpp
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Handler/CalleeSavedHandler.cpp
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Handler/CalleeSavedHandler.cpp
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Handler/LegalizeImmediates.cpp
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Handler/LegalizeImmediates.cpp
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Handler/PrologueEpilogueInsertion.cpp
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Handler/PrologueEpilogueInsertion.cpp
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459
src/backend/RISCv64/RISCv64LinearScan.cpp
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459
src/backend/RISCv64/RISCv64LinearScan.cpp
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@@ -0,0 +1,459 @@
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#include "RISCv64LinearScan.h"
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#include "RISCv64LLIR.h"
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#include "RISCv64ISel.h"
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#include <iostream>
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#include <set>
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extern int DEBUG;
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namespace sysy {
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RISCv64LinearScan::RISCv64LinearScan(MachineFunction* mfunc)
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: MFunc(mfunc),
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ISel(mfunc->getISel()),
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vreg_type_map(ISel->getVRegTypeMap()) {
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// 初始化可用的物理寄存器池，与图着色版本保持一致
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// 整数寄存器
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allocable_int_regs = {
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PhysicalReg::T0, PhysicalReg::T1, PhysicalReg::T2, PhysicalReg::T3, PhysicalReg::T4, /*T5保留作为大立即数加载寄存器*/ PhysicalReg::T6,
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PhysicalReg::A0, PhysicalReg::A1, PhysicalReg::A2, PhysicalReg::A3, PhysicalReg::A4, PhysicalReg::A5, PhysicalReg::A6, PhysicalReg::A7,
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PhysicalReg::S1, PhysicalReg::S2, PhysicalReg::S3, PhysicalReg::S4, PhysicalReg::S5, PhysicalReg::S6, PhysicalReg::S7,
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PhysicalReg::S8, PhysicalReg::S9, PhysicalReg::S10, PhysicalReg::S11,
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};
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// 浮点寄存器
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allocable_fp_regs = {
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PhysicalReg::F0, PhysicalReg::F1, PhysicalReg::F2, PhysicalReg::F3, PhysicalReg::F4, PhysicalReg::F5, PhysicalReg::F6, PhysicalReg::F7,
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PhysicalReg::F10, PhysicalReg::F11, PhysicalReg::F12, PhysicalReg::F13, PhysicalReg::F14, PhysicalReg::F15, PhysicalReg::F16, PhysicalReg::F17,
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PhysicalReg::F8, PhysicalReg::F9, PhysicalReg::F18, PhysicalReg::F19, PhysicalReg::F20, PhysicalReg::F21, PhysicalReg::F22,
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PhysicalReg::F23, PhysicalReg::F24, PhysicalReg::F25, PhysicalReg::F26, PhysicalReg::F27,
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PhysicalReg::F28, PhysicalReg::F29, PhysicalReg::F30, PhysicalReg::F31,
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};
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// 新增：识别所有通过寄存器传递的参数，并建立vreg到物理寄存器(preg)的映射
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// 这等同于图着色算法中的“预着色”步骤。
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if (MFunc->getFunc()) {
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int int_arg_idx = 0;
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int fp_arg_idx = 0;
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for (Argument* arg : MFunc->getFunc()->getArguments()) {
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unsigned arg_vreg = ISel->getVReg(arg);
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if (arg->getType()->isFloat()) {
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if (fp_arg_idx < 8) { // fa0-fa7
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auto preg = static_cast<PhysicalReg>(static_cast<int>(PhysicalReg::F10) + fp_arg_idx);
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abi_vreg_map[arg_vreg] = preg;
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fp_arg_idx++;
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}
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} else { // 整数或指针
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if (int_arg_idx < 8) { // a0-a7
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auto preg = static_cast<PhysicalReg>(static_cast<int>(PhysicalReg::A0) + int_arg_idx);
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abi_vreg_map[arg_vreg] = preg;
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int_arg_idx++;
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}
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}
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}
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}
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}
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void RISCv64LinearScan::run() {
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if (DEBUG) std::cerr << "===== Running Linear Scan Register Allocation for function: " << MFunc->getName() << " =====\n";
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bool changed = true;
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while(changed) {
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// 1. 准备阶段
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linearizeBlocks();
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computeLiveIntervals();
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// 2. 执行线性扫描
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changed = linearScan();
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// 3. 如果有溢出，重写代码，然后下一轮重新开始
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if (changed) {
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rewriteProgram();
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if (DEBUG) std::cerr << "--- Spilling detected, re-running linear scan ---\n";
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}
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}
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// 4. 将最终分配结果应用到机器指令
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applyAllocation();
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// 5. 收集用到的被调用者保存寄存器
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MFunc->getFrameInfo().vreg_to_preg_map = this->vreg_to_preg_map;
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collectUsedCalleeSavedRegs();
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if (DEBUG) std::cerr << "===== Finished Linear Scan Register Allocation =====\n\n";
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}
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// 步骤 1.1: 对基本块进行线性化，这里我们简单地按现有顺序排列
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void RISCv64LinearScan::linearizeBlocks() {
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linear_order_blocks.clear();
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for (auto& mbb : MFunc->getBlocks()) {
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linear_order_blocks.push_back(mbb.get());
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}
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}
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// 步骤 1.2: 计算活跃区间
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void RISCv64LinearScan::computeLiveIntervals() {
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instr_numbering.clear();
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live_intervals.clear();
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unhandled.clear();
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// a. 对所有指令进行线性编号
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int num = 0;
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for (auto* mbb : linear_order_blocks) {
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for (auto& instr : mbb->getInstructions()) {
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instr_numbering[instr.get()] = num;
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num += 2; // 指令编号间隔为2，方便在溢出重写时插入指令
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}
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}
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// b. (新逻辑) 遍历所有指令，记录每个vreg首次和末次出现的位置
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std::map<unsigned, std::pair<int, int>> vreg_ranges; // vreg -> {first_instr_num, last_instr_num}
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for (auto* mbb : linear_order_blocks) {
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for (auto& instr_ptr : mbb->getInstructions()) {
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const MachineInstr* instr = instr_ptr.get();
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int instr_num = instr_numbering.at(instr);
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std::set<unsigned> use, def;
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getInstrUseDef(instr, use, def);
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// 合并use和def集合，获取本条指令涉及的所有vreg
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auto all_vregs = use;
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all_vregs.insert(def.begin(), def.end());
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// 更新每个vreg的区间边界
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for (unsigned vreg : all_vregs) {
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if (vreg_ranges.find(vreg) == vreg_ranges.end()) {
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// 第一次见到这个vreg，记录首次和末次位置
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vreg_ranges[vreg] = {instr_num, instr_num};
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} else {
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// 更新末次位置
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vreg_ranges[vreg].second = std::max(vreg_ranges[vreg].second, instr_num);
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}
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}
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}
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}
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// c. 根据记录的边界，创建LiveInterval对象
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for (auto const& [vreg, range] : vreg_ranges) {
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live_intervals.emplace(vreg, LiveInterval(vreg));
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live_intervals.at(vreg).start = range.first;
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live_intervals.at(vreg).end = range.second;
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}
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// d. 将所有计算出的活跃区间放入 unhandled 列表
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for (auto& pair : live_intervals) {
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unhandled.push_back(&pair.second);
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}
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std::sort(unhandled.begin(), unhandled.end(), [](const LiveInterval* a, const LiveInterval* b){
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return a->start < b->start;
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});
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}
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// 步骤 2: 线性扫描主算法
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bool RISCv64LinearScan::linearScan() {
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// 初始化/重置状态
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active.clear();
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spilled_vregs.clear();
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vreg_to_preg_map.clear();
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free_int_regs.clear();
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free_fp_regs.clear();
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free_int_regs.insert(allocable_int_regs.begin(), allocable_int_regs.end());
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free_fp_regs.insert(allocable_fp_regs.begin(), allocable_fp_regs.end());
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// 1. 将ABI参数的vreg直接分配给其固定的物理寄存器
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vreg_to_preg_map.insert(abi_vreg_map.begin(), abi_vreg_map.end());
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// 2. 从unhandled列表中移除这些ABI参数区间，并将其加入active列表
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std::vector<LiveInterval*> normal_unhandled;
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for(LiveInterval* interval : unhandled) {
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if(abi_vreg_map.count(interval->vreg)) {
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// 这是一个ABI参数区间，它已经被“预分配”
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active.push_back(interval);
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// 从空闲池中移除对应的物理寄存器
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PhysicalReg preg = abi_vreg_map.at(interval->vreg);
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if (isFPVReg(interval->vreg)) {
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free_fp_regs.erase(preg);
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} else {
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free_int_regs.erase(preg);
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}
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} else {
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// 这是一个普通区间，留待后续处理
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normal_unhandled.push_back(interval);
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}
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}
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unhandled = normal_unhandled; // 更新unhandled列表，只包含普通区间
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// 3. 对active列表（现在只包含ABI参数）按结束点排序
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std::sort(active.begin(), active.end(), [](const LiveInterval* a, const LiveInterval* b){
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return a->end < b->end;
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});
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for (LiveInterval* current : unhandled) {
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// a. 检查并释放 active 列表中已经结束的区间
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std::vector<LiveInterval*> new_active;
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for (LiveInterval* active_interval : active) {
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if (active_interval->end < current->start) {
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// 此区间已结束，释放其物理寄存器
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PhysicalReg preg = vreg_to_preg_map.at(active_interval->vreg);
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if (isFPVReg(active_interval->vreg)) free_fp_regs.insert(preg);
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else free_int_regs.insert(preg);
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} else {
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new_active.push_back(active_interval);
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}
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}
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active = new_active;
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// b. 尝试为当前区间分配寄存器
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chooseRegForInterval(current);
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}
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return !spilled_vregs.empty();
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}
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void RISCv64LinearScan::chooseRegForInterval(LiveInterval* current) {
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bool is_fp = isFPVReg(current->vreg);
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auto& free_regs = is_fp ? free_fp_regs : free_int_regs;
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if (!free_regs.empty()) {
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// 有可用寄存器
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PhysicalReg preg = *free_regs.begin();
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free_regs.erase(free_regs.begin());
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vreg_to_preg_map[current->vreg] = preg;
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active.push_back(current);
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// 保持 active 列表按结束点排序
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std::sort(active.begin(), active.end(), [](const LiveInterval* a, const LiveInterval* b){
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return a->end < b->end;
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});
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} else {
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// 没有可用寄存器，需要溢出
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spillAtInterval(current);
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}
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}
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void RISCv64LinearScan::spillAtInterval(LiveInterval* current) {
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// 启发式：比较当前区间和 active 列表中结束点最晚的区间
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LiveInterval* spill_candidate = active.back(); // active已按end排序，最后一个就是结束最晚的
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if (spill_candidate->end > current->end) {
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// active中的区间结束得更晚，溢出它
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PhysicalReg preg = vreg_to_preg_map.at(spill_candidate->vreg);
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// 将被溢出区间的物理寄存器分配给当前区间
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vreg_to_preg_map[current->vreg] = preg;
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// 更新 active 列表
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active.pop_back(); // 移除被溢出的
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active.push_back(current); // 加入当前的
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std::sort(active.begin(), active.end(), [](const LiveInterval* a, const LiveInterval* b){
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return a->end < b->end;
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});
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spilled_vregs.insert(spill_candidate->vreg);
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if(DEBUG) std::cerr << " Spilling vreg" << spill_candidate->vreg << " to make room for vreg" << current->vreg << "\n";
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} else {
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// 当前区间结束得更晚，直接溢出当前区间
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spilled_vregs.insert(current->vreg);
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if(DEBUG) std::cerr << " Spilling current vreg" << current->vreg << "\n";
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}
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}
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// 步骤 3: 重写程序，插入溢出代码
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void RISCv64LinearScan::rewriteProgram() {
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StackFrameInfo& frame_info = MFunc->getFrameInfo();
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int spill_offset = frame_info.locals_size; // 溢出区域接在局部变量之后
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for (unsigned vreg : spilled_vregs) {
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if (frame_info.spill_offsets.count(vreg)) continue; // 避免重复分配
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int size = isFPVReg(vreg) ? 4 : (vreg_type_map.at(vreg)->isPointer() ? 8 : 4);
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spill_offset += size;
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spill_offset = (spill_offset + 7) & ~7; // 8字节对齐
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frame_info.spill_offsets[vreg] = -(16 + spill_offset);
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}
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frame_info.spill_size = spill_offset - frame_info.locals_size;
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for (auto& mbb : MFunc->getBlocks()) {
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auto& instrs = mbb->getInstructions();
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std::vector<std::unique_ptr<MachineInstr>> new_instrs;
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for (auto it = instrs.begin(); it != instrs.end(); ++it) {
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auto& instr = *it;
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std::set<unsigned> use, def;
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getInstrUseDef(instr.get(), use, def);
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// 为每个溢出的 use 创建 load
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for (unsigned old_vreg : use) {
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if (spilled_vregs.count(old_vreg)) {
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Type* type = vreg_type_map.at(old_vreg);
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unsigned new_temp_vreg = ISel->getNewVReg(type);
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RVOpcodes load_op = isFPVReg(old_vreg) ? RVOpcodes::FLW : (type->isPointer() ? RVOpcodes::LD : RVOpcodes::LW);
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auto load = std::make_unique<MachineInstr>(load_op);
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load->addOperand(std::make_unique<RegOperand>(new_temp_vreg));
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load->addOperand(std::make_unique<MemOperand>(
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std::make_unique<RegOperand>(PhysicalReg::S0),
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std::make_unique<ImmOperand>(frame_info.spill_offsets.at(old_vreg))
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));
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new_instrs.push_back(std::move(load));
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// 替换原指令中的 use
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for(auto& op : instr->getOperands()) {
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if(op->getKind() == MachineOperand::KIND_REG) {
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auto reg_op = static_cast<RegOperand*>(op.get());
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if(reg_op->isVirtual() && reg_op->getVRegNum() == old_vreg) {
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reg_op->setVRegNum(new_temp_vreg);
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}
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} else if(op->getKind() == MachineOperand::KIND_MEM) {
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auto mem_op = static_cast<MemOperand*>(op.get());
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auto base_reg = mem_op->getBase();
|
||||||
|
if(base_reg->isVirtual() && base_reg->getVRegNum() == old_vreg) {
|
||||||
|
base_reg->setVRegNum(new_temp_vreg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
new_instrs.push_back(std::move(instr));
|
||||||
|
|
||||||
|
// 为每个溢出的 def 创建 store
|
||||||
|
for (unsigned old_vreg : def) {
|
||||||
|
if (spilled_vregs.count(old_vreg)) {
|
||||||
|
Type* type = vreg_type_map.at(old_vreg);
|
||||||
|
unsigned new_temp_vreg = ISel->getNewVReg(type);
|
||||||
|
|
||||||
|
// 替换原指令中的 def
|
||||||
|
for(auto& op : new_instrs.back()->getOperands()) {
|
||||||
|
if(op->getKind() == MachineOperand::KIND_REG) {
|
||||||
|
auto reg_op = static_cast<RegOperand*>(op.get());
|
||||||
|
if(reg_op->isVirtual() && reg_op->getVRegNum() == old_vreg) {
|
||||||
|
reg_op->setVRegNum(new_temp_vreg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
RVOpcodes store_op = isFPVReg(old_vreg) ? RVOpcodes::FSW : (type->isPointer() ? RVOpcodes::SD : RVOpcodes::SW);
|
||||||
|
auto store = std::make_unique<MachineInstr>(store_op);
|
||||||
|
store->addOperand(std::make_unique<RegOperand>(new_temp_vreg));
|
||||||
|
store->addOperand(std::make_unique<MemOperand>(
|
||||||
|
std::make_unique<RegOperand>(PhysicalReg::S0),
|
||||||
|
std::make_unique<ImmOperand>(frame_info.spill_offsets.at(old_vreg))
|
||||||
|
));
|
||||||
|
new_instrs.push_back(std::move(store));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
instrs = std::move(new_instrs);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// 步骤 4: 应用最终分配结果
|
||||||
|
void RISCv64LinearScan::applyAllocation() {
|
||||||
|
for (auto& mbb : MFunc->getBlocks()) {
|
||||||
|
for (auto& instr_ptr : mbb->getInstructions()) {
|
||||||
|
for (auto& op_ptr : instr_ptr->getOperands()) {
|
||||||
|
if (op_ptr->getKind() == MachineOperand::KIND_REG) {
|
||||||
|
auto reg_op = static_cast<RegOperand*>(op_ptr.get());
|
||||||
|
if (reg_op->isVirtual()) {
|
||||||
|
unsigned vreg = reg_op->getVRegNum();
|
||||||
|
if (vreg_to_preg_map.count(vreg)) {
|
||||||
|
reg_op->setPReg(vreg_to_preg_map.at(vreg));
|
||||||
|
} else {
|
||||||
|
// 如果一个vreg最终没有颜色，这通常意味着它是一个短生命周期的临时变量
|
||||||
|
// 在溢出重写中产生，但在下一轮分配前就被优化掉了。
|
||||||
|
// 或者是一个从未被使用的定义。
|
||||||
|
// 给他一个临时寄存器以防万一。
|
||||||
|
reg_op->setPReg(PhysicalReg::T5);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else if (op_ptr->getKind() == MachineOperand::KIND_MEM) {
|
||||||
|
auto mem_op = static_cast<MemOperand*>(op_ptr.get());
|
||||||
|
auto reg_op = mem_op->getBase();
|
||||||
|
if (reg_op->isVirtual()) {
|
||||||
|
unsigned vreg = reg_op->getVRegNum();
|
||||||
|
if (vreg_to_preg_map.count(vreg)) {
|
||||||
|
reg_op->setPReg(vreg_to_preg_map.at(vreg));
|
||||||
|
} else {
|
||||||
|
reg_op->setPReg(PhysicalReg::T5);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// 辅助函数: 获取指令的use/def集合 (仅虚拟寄存器)
|
||||||
|
void RISCv64LinearScan::getInstrUseDef(const MachineInstr* instr, std::set<unsigned>& use, std::set<unsigned>& def) {
|
||||||
|
// 这个函数与图着色版本中的 getInstrUseDef 逻辑完全相同，此处直接复用
|
||||||
|
auto opcode = instr->getOpcode();
|
||||||
|
const auto& operands = instr->getOperands();
|
||||||
|
|
||||||
|
static const std::map<RVOpcodes, std::pair<std::vector<int>, std::vector<int>>> op_info = {
|
||||||
|
{RVOpcodes::ADD, {{0}, {1, 2}}}, {RVOpcodes::SUB, {{0}, {1, 2}}}, {RVOpcodes::MUL, {{0}, {1, 2}}},
|
||||||
|
{RVOpcodes::DIV, {{0}, {1, 2}}}, {RVOpcodes::REM, {{0}, {1, 2}}}, {RVOpcodes::ADDW, {{0}, {1, 2}}},
|
||||||
|
{RVOpcodes::SUBW, {{0}, {1, 2}}}, {RVOpcodes::MULW, {{0}, {1, 2}}}, {RVOpcodes::DIVW, {{0}, {1, 2}}},
|
||||||
|
{RVOpcodes::REMW, {{0}, {1, 2}}}, {RVOpcodes::SLT, {{0}, {1, 2}}}, {RVOpcodes::SLTU, {{0}, {1, 2}}},
|
||||||
|
{RVOpcodes::ADDI, {{0}, {1}}}, {RVOpcodes::ADDIW, {{0}, {1}}}, {RVOpcodes::XORI, {{0}, {1}}},
|
||||||
|
{RVOpcodes::SLTI, {{0}, {1}}}, {RVOpcodes::SLTIU, {{0}, {1}}}, {RVOpcodes::LB, {{0}, {}}},
|
||||||
|
{RVOpcodes::LH, {{0}, {}}}, {RVOpcodes::LW, {{0}, {}}}, {RVOpcodes::LD, {{0}, {}}},
|
||||||
|
{RVOpcodes::LBU, {{0}, {}}}, {RVOpcodes::LHU, {{0}, {}}}, {RVOpcodes::LWU, {{0}, {}}},
|
||||||
|
{RVOpcodes::FLW, {{0}, {}}}, {RVOpcodes::FLD, {{0}, {}}}, {RVOpcodes::SB, {{}, {0, 1}}},
|
||||||
|
{RVOpcodes::SH, {{}, {0, 1}}}, {RVOpcodes::SW, {{}, {0, 1}}}, {RVOpcodes::SD, {{}, {0, 1}}},
|
||||||
|
{RVOpcodes::FSW, {{}, {0, 1}}}, {RVOpcodes::FSD, {{}, {0, 1}}}, {RVOpcodes::BEQ, {{}, {0, 1}}},
|
||||||
|
{RVOpcodes::BNE, {{}, {0, 1}}}, {RVOpcodes::BLT, {{}, {0, 1}}}, {RVOpcodes::BGE, {{}, {0, 1}}},
|
||||||
|
{RVOpcodes::JALR, {{0}, {1}}}, {RVOpcodes::LI, {{0}, {}}}, {RVOpcodes::LA, {{0}, {}}},
|
||||||
|
{RVOpcodes::MV, {{0}, {1}}}, {RVOpcodes::SEQZ, {{0}, {1}}}, {RVOpcodes::SNEZ, {{0}, {1}}},
|
||||||
|
{RVOpcodes::RET, {{}, {}}}, {RVOpcodes::FADD_S, {{0}, {1, 2}}}, {RVOpcodes::FSUB_S, {{0}, {1, 2}}},
|
||||||
|
{RVOpcodes::FMUL_S, {{0}, {1, 2}}}, {RVOpcodes::FDIV_S, {{0}, {1, 2}}}, {RVOpcodes::FEQ_S, {{0}, {1, 2}}},
|
||||||
|
{RVOpcodes::FLT_S, {{0}, {1, 2}}}, {RVOpcodes::FLE_S, {{0}, {1, 2}}}, {RVOpcodes::FCVT_S_W, {{0}, {1}}},
|
||||||
|
{RVOpcodes::FCVT_W_S, {{0}, {1}}}, {RVOpcodes::FMV_S, {{0}, {1}}}, {RVOpcodes::FMV_W_X, {{0}, {1}}},
|
||||||
|
{RVOpcodes::FMV_X_W, {{0}, {1}}}, {RVOpcodes::FNEG_S, {{0}, {1}}}
|
||||||
|
};
|
||||||
|
|
||||||
|
auto get_vreg_id_if_virtual = [&](const MachineOperand* op, std::set<unsigned>& s) {
|
||||||
|
if (op->getKind() == MachineOperand::KIND_REG) {
|
||||||
|
auto reg_op = static_cast<const RegOperand*>(op);
|
||||||
|
if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
|
||||||
|
} else if (op->getKind() == MachineOperand::KIND_MEM) {
|
||||||
|
auto mem_op = static_cast<const MemOperand*>(op);
|
||||||
|
auto reg_op = mem_op->getBase();
|
||||||
|
if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
if (op_info.count(opcode)) {
|
||||||
|
const auto& info = op_info.at(opcode);
|
||||||
|
for (int idx : info.first) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), def);
|
||||||
|
for (int idx : info.second) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), use);
|
||||||
|
for (const auto& op : operands) if (op->getKind() == MachineOperand::KIND_MEM) get_vreg_id_if_virtual(op.get(), use);
|
||||||
|
} else if (opcode == RVOpcodes::CALL) {
|
||||||
|
if (!operands.empty() && operands[0]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[0].get(), def);
|
||||||
|
for (size_t i = 1; i < operands.size(); ++i) if (operands[i]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[i].get(), use);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// 辅助函数: 判断是否为浮点vreg
|
||||||
|
bool RISCv64LinearScan::isFPVReg(unsigned vreg) const {
|
||||||
|
return vreg_type_map.count(vreg) && vreg_type_map.at(vreg)->isFloat();
|
||||||
|
}
|
||||||
|
|
||||||
|
// 辅助函数: 收集被使用的被调用者保存寄存器
|
||||||
|
void RISCv64LinearScan::collectUsedCalleeSavedRegs() {
|
||||||
|
StackFrameInfo& frame_info = MFunc->getFrameInfo();
|
||||||
|
frame_info.used_callee_saved_regs.clear();
|
||||||
|
|
||||||
|
const auto& callee_saved_int = getCalleeSavedIntRegs();
|
||||||
|
const auto& callee_saved_fp = getCalleeSavedFpRegs();
|
||||||
|
std::set<PhysicalReg> callee_saved_set(callee_saved_int.begin(), callee_saved_int.end());
|
||||||
|
callee_saved_set.insert(callee_saved_fp.begin(), callee_saved_fp.end());
|
||||||
|
callee_saved_set.insert(PhysicalReg::S0); // s0总是被用作帧指针
|
||||||
|
|
||||||
|
for(const auto& pair : vreg_to_preg_map) {
|
||||||
|
PhysicalReg preg = pair.second;
|
||||||
|
if(callee_saved_set.count(preg)) {
|
||||||
|
frame_info.used_callee_saved_regs.insert(preg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace sysy
|
||||||
@@ -55,41 +55,12 @@ void RISCv64RegAlloc::run() {
|
|||||||
|
|
||||||
if (DEBUG) std::cerr << "===== Running Graph Coloring Register Allocation for function: " << MFunc->getName() << " =====\n";
|
if (DEBUG) std::cerr << "===== Running Graph Coloring Register Allocation for function: " << MFunc->getName() << " =====\n";
|
||||||
|
|
||||||
const int MAX_ITERATIONS = 50;
|
while (true) {
|
||||||
int iteration = 0;
|
|
||||||
|
|
||||||
while (iteration++ < MAX_ITERATIONS) {
|
|
||||||
if (doAllocation()) {
|
if (doAllocation()) {
|
||||||
break;
|
break;
|
||||||
} else {
|
} else {
|
||||||
rewriteProgram();
|
rewriteProgram();
|
||||||
if (DEBUG) std::cerr << "--- Spilling detected, re-running allocation (iteration " << iteration << ") ---\n";
|
if (DEBUG) std::cerr << "--- Spilling detected, re-running allocation ---\n";
|
||||||
|
|
||||||
if (iteration >= MAX_ITERATIONS) {
|
|
||||||
std::cerr << "ERROR: Register allocation failed to converge after " << MAX_ITERATIONS << " iterations\n";
|
|
||||||
std::cerr << " Spill worklist size: " << spillWorklist.size() << "\n";
|
|
||||||
std::cerr << " Total nodes: " << (initial.size() + coloredNodes.size()) << "\n";
|
|
||||||
|
|
||||||
// Emergency spill remaining nodes to break the loop
|
|
||||||
std::cerr << " Emergency spilling remaining spill worklist nodes...\n";
|
|
||||||
for (unsigned node : spillWorklist) {
|
|
||||||
spilledNodes.insert(node);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Also spill any nodes that didn't get colors
|
|
||||||
std::set<unsigned> uncolored;
|
|
||||||
for (unsigned node : initial) {
|
|
||||||
if (color_map.find(node) == color_map.end()) {
|
|
||||||
uncolored.insert(node);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
for (unsigned node : uncolored) {
|
|
||||||
spilledNodes.insert(node);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Force completion
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
81
src/include/backend/RISCv64/RISCv64LinearScan.h
Normal file
81
src/include/backend/RISCv64/RISCv64LinearScan.h
Normal file
@@ -0,0 +1,81 @@
|
|||||||
|
#ifndef RISCV64_LINEARSCAN_H
|
||||||
|
#define RISCV64_LINEARSCAN_H
|
||||||
|
|
||||||
|
#include "RISCv64LLIR.h"
|
||||||
|
#include "RISCv64ISel.h"
|
||||||
|
#include <vector>
|
||||||
|
#include <map>
|
||||||
|
#include <set>
|
||||||
|
#include <algorithm>
|
||||||
|
|
||||||
|
namespace sysy {
|
||||||
|
|
||||||
|
// 前向声明
|
||||||
|
class MachineBasicBlock;
|
||||||
|
class MachineFunction;
|
||||||
|
class RISCv64ISel;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 表示一个虚拟寄存器的活跃区间。
|
||||||
|
* 包含起始和结束指令编号。为了简化，我们不处理有“洞”的区间。
|
||||||
|
*/
|
||||||
|
struct LiveInterval {
|
||||||
|
unsigned vreg = 0;
|
||||||
|
int start = -1;
|
||||||
|
int end = -1;
|
||||||
|
|
||||||
|
LiveInterval(unsigned vreg) : vreg(vreg) {}
|
||||||
|
|
||||||
|
// 用于排序，按起始点从小到大
|
||||||
|
bool operator<(const LiveInterval& other) const {
|
||||||
|
return start < other.start;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
class RISCv64LinearScan {
|
||||||
|
public:
|
||||||
|
RISCv64LinearScan(MachineFunction* mfunc);
|
||||||
|
void run();
|
||||||
|
|
||||||
|
private:
|
||||||
|
// --- 核心算法流程 ---
|
||||||
|
void linearizeBlocks();
|
||||||
|
void computeLiveIntervals();
|
||||||
|
bool linearScan();
|
||||||
|
void rewriteProgram();
|
||||||
|
void applyAllocation();
|
||||||
|
void chooseRegForInterval(LiveInterval* current);
|
||||||
|
void spillAtInterval(LiveInterval* current);
|
||||||
|
|
||||||
|
// --- 辅助函数 ---
|
||||||
|
void getInstrUseDef(const MachineInstr* instr, std::set<unsigned>& use, std::set<unsigned>& def);
|
||||||
|
bool isFPVReg(unsigned vreg) const;
|
||||||
|
void collectUsedCalleeSavedRegs();
|
||||||
|
|
||||||
|
MachineFunction* MFunc;
|
||||||
|
RISCv64ISel* ISel;
|
||||||
|
|
||||||
|
// --- 线性扫描数据结构 ---
|
||||||
|
std::vector<MachineBasicBlock*> linear_order_blocks;
|
||||||
|
std::map<const MachineInstr*, int> instr_numbering;
|
||||||
|
std::map<unsigned, LiveInterval> live_intervals;
|
||||||
|
|
||||||
|
std::vector<LiveInterval*> unhandled;
|
||||||
|
std::vector<LiveInterval*> active; // 活跃且已分配物理寄存器的区间
|
||||||
|
|
||||||
|
std::set<unsigned> spilled_vregs; // 记录在本轮被决定溢出的vreg
|
||||||
|
|
||||||
|
// --- 寄存器池和分配结果 ---
|
||||||
|
std::vector<PhysicalReg> allocable_int_regs;
|
||||||
|
std::vector<PhysicalReg> allocable_fp_regs;
|
||||||
|
std::set<PhysicalReg> free_int_regs;
|
||||||
|
std::set<PhysicalReg> free_fp_regs;
|
||||||
|
std::map<unsigned, PhysicalReg> vreg_to_preg_map;
|
||||||
|
std::map<unsigned, PhysicalReg> abi_vreg_map;
|
||||||
|
|
||||||
|
const std::map<unsigned, Type*>& vreg_type_map;
|
||||||
|
};
|
||||||
|
|
||||||
|
} // namespace sysy
|
||||||
|
|
||||||
|
#endif // RISCV64_LINEARSCAN_H
|
||||||
Reference in New Issue
Block a user