From 384f7c548b793b2227e3342a9fce5bff1428fd52 Mon Sep 17 00:00:00 2001 From: Lixuanwang Date: Fri, 1 Aug 2025 23:18:53 +0800 Subject: [PATCH] =?UTF-8?q?[backend-IRC]=E6=B7=BB=E5=8A=A0=E4=BA=86?= =?UTF-8?q?=E4=B8=89=E7=BA=A7=E8=B0=83=E8=AF=95=E6=89=93=E5=8D=B0=E9=80=BB?= =?UTF-8?q?=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/backend/RISCv64/RISCv64RegAlloc.cpp | 173 ++++++++---------- src/include/backend/RISCv64/RISCv64RegAlloc.h | 4 +- src/sysyc.cpp | 2 + 3 files changed, 85 insertions(+), 94 deletions(-) diff --git a/src/backend/RISCv64/RISCv64RegAlloc.cpp b/src/backend/RISCv64/RISCv64RegAlloc.cpp index 3eed7dd..76f003b 100644 --- a/src/backend/RISCv64/RISCv64RegAlloc.cpp +++ b/src/backend/RISCv64/RISCv64RegAlloc.cpp @@ -1,5 +1,3 @@ -// in file: RISCv64RegAlloc.cpp - #include "RISCv64RegAlloc.h" #include "RISCv64AsmPrinter.h" #include @@ -263,7 +261,7 @@ void RISCv64RegAlloc::build() { getInstrUseDef_Liveness(instr, use, def); // 调试输出 use 和 def (保留您的调试逻辑) - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "Instr:"; printer_inside_build.printInstruction(instr_ptr.get(), true); auto print_set = [this](const VRegSet& s, const std::string& name) { @@ -278,7 +276,7 @@ void RISCv64RegAlloc::build() { for (unsigned v : use) { if (!coloredNodes.count(v) && !precolored.count(v)) { initial.insert(v); - } else if (DEEPDEBUG) { + } else if ((DEEPDEBUG && initial.size() < DEBUGLENGTH) || DEEPERDEBUG) { // 这里的调试信息可以更精确 if (precolored.count(v)) { std::cerr << "Skipping " << regIdToString(v) << " because it is a physical register.\n"; @@ -290,7 +288,7 @@ void RISCv64RegAlloc::build() { for (unsigned v : def) { if (!coloredNodes.count(v) && !precolored.count(v)) { initial.insert(v); - } else if (DEEPDEBUG) { + } else if ((DEEPDEBUG && initial.size() < DEBUGLENGTH) || DEEPERDEBUG) { if (precolored.count(v)) { std::cerr << "Skipping " << regIdToString(v) << " because it is a physical register.\n"; } else { @@ -302,9 +300,20 @@ void RISCv64RegAlloc::build() { } if (DEEPDEBUG) { - std::cerr << "Initial set after build: { "; - for (unsigned v : initial) std::cerr << regIdToString(v) << " "; - std::cerr << "}\n"; + if (initial.size() > DEBUGLENGTH && !DEEPERDEBUG) { + std::cerr << "Initial set too large, showing first " << DEBUGLENGTH << " elements:\n"; + } + std::cerr << "Initial set (" << initial.size() << "): { "; + unsigned count = 0; + for (unsigned v : initial) { + if (count++ >= DEBUGLENGTH && !DEEPERDEBUG) break; // 限制输出数量 + std::cerr << regIdToString(v) << " "; + } + if (count < initial.size()) { + std::cerr << "... (total " << initial.size() << " elements)\n"; + } else { + std::cerr << "}\n"; + } } // 2. 为所有参与图构建的虚拟寄存器（initial + coloredNodes）初始化数据结构 @@ -331,7 +340,7 @@ void RISCv64RegAlloc::build() { const VRegSet& live_out = live_out_map.at(instr); // 保留您的指令级调试输出 - if (DEEPDEBUG) { + if (DEEPERDEBUG) { RISCv64AsmPrinter temp_printer(MFunc); temp_printer.setStream(std::cerr); std::cerr << "Instr: "; @@ -417,7 +426,7 @@ void RISCv64RegAlloc::makeWorklist() { std::cerr << "Error: degree not initialized for %vreg" << n << "\n"; continue; } - if (DEEPDEBUG) { + if ((DEEPDEBUG && initial.size() < DEBUGLENGTH) || DEEPERDEBUG) { std::cerr << "Assigning %vreg" << n << " (degree=" << degree.at(n) << ", moveRelated=" << moveRelated(n) << ")\n"; } @@ -429,7 +438,7 @@ void RISCv64RegAlloc::makeWorklist() { simplifyWorklist.insert(n); } } - if (DEEPDEBUG) std::cerr << "--------------------------------\n"; + if (DEEPDEBUG || DEEPERDEBUG) std::cerr << "--------------------------------\n"; initial.clear(); } @@ -437,7 +446,7 @@ void RISCv64RegAlloc::makeWorklist() { void RISCv64RegAlloc::simplify() { unsigned n = *simplifyWorklist.begin(); simplifyWorklist.erase(simplifyWorklist.begin()); - if (DEEPDEBUG) std::cerr << "[Simplify] Popped %vreg" << n << ", pushing to stack.\n"; + if (DEEPERDEBUG) std::cerr << "[Simplify] Popped %vreg" << n << ", pushing to stack.\n"; selectStack.push_back(n); for (unsigned m : adjacent(n)) { decrementDegree(m); @@ -455,19 +464,19 @@ void RISCv64RegAlloc::coalesce() { unsigned u, v; if (precolored.count(y)) { u = y; v = x; } else { u = x; v = y; } - if (DEEPDEBUG) std::cerr << "[Coalesce] Processing move between " << regIdToString(x) + if (DEEPERDEBUG) std::cerr << "[Coalesce] Processing move between " << regIdToString(x) << " and " << regIdToString(y) << " (aliases " << regIdToString(u) << ", " << regIdToString(v) << ").\n"; if (u == v) { - if (DEEPDEBUG) std::cerr << " -> Trivial coalesce (u == v).\n"; + if (DEEPERDEBUG) std::cerr << " -> Trivial coalesce (u == v).\n"; coalescedMoves.insert(move); addWorklist(u); return; // 处理完毕，提前返回 } if (isFPVReg(u) != isFPVReg(v)) { - if (DEEPDEBUG) std::cerr << " -> Constrained (type mismatch: " << regIdToString(u) << " is " + if (DEEPERDEBUG) std::cerr << " -> Constrained (type mismatch: " << regIdToString(u) << " is " << (isFPVReg(u) ? "float" : "int") << ", " << regIdToString(v) << " is " << (isFPVReg(v) ? "float" : "int") << ").\n"; constrainedMoves.insert(move); @@ -481,7 +490,7 @@ void RISCv64RegAlloc::coalesce() { bool pre_interfere = adjList.at(v).count(u); if (pre_interfere) { - if (DEEPDEBUG) std::cerr << " -> Constrained (nodes already interfere).\n"; + if (DEEPERDEBUG) std::cerr << " -> Constrained (nodes already interfere).\n"; constrainedMoves.insert(move); addWorklist(u); addWorklist(v); @@ -493,13 +502,13 @@ void RISCv64RegAlloc::coalesce() { if (is_u_precolored) { // --- 场景1：u是物理寄存器，使用 George 启发式 --- - if (DEEPDEBUG) std::cerr << " -> Trying George Heuristic (u is precolored)...\n"; + if (DEEPERDEBUG) std::cerr << " -> Trying George Heuristic (u is precolored)...\n"; // ==================== [展开的 std::all_of 逻辑] ==================== // 步骤 1: 独立调用 adjacent(v) 获取邻居集合 VRegSet neighbors_of_v = adjacent(v); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << " - Neighbors of " << regIdToString(v) << " to check are (" << neighbors_of_v.size() << "): { "; for (unsigned id : neighbors_of_v) std::cerr << regIdToString(id) << " "; std::cerr << "}\n"; @@ -508,14 +517,14 @@ void RISCv64RegAlloc::coalesce() { // 步骤 2: 使用显式的 for 循环来代替 std::all_of bool george_ok = true; // 默认假设成功，任何一个邻居失败都会将此设为 false for (unsigned t : neighbors_of_v) { - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << " - Checking neighbor " << regIdToString(t) << ":\n"; } // 步骤 3: 独立调用启发式函数 bool heuristic_result = georgeHeuristic(t, u); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << " - georgeHeuristic(" << regIdToString(t) << ", " << regIdToString(u) << ") -> " << (heuristic_result ? "OK" : "FAIL") << "\n"; } @@ -525,7 +534,7 @@ void RISCv64RegAlloc::coalesce() { } } - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << " -> George Heuristic final result: " << (george_ok ? "OK" : "FAIL") << "\n"; } // ================================================================= @@ -536,10 +545,10 @@ void RISCv64RegAlloc::coalesce() { } else { // --- 场景2：u和v都是虚拟寄存器，使用 Briggs 启发式 --- - if (DEEPDEBUG) std::cerr << " -> Trying Briggs Heuristic (u and v are virtual)...\n"; + if (DEEPERDEBUG) std::cerr << " -> Trying Briggs Heuristic (u and v are virtual)...\n"; bool briggs_ok = briggsHeuristic(u, v); - if (DEEPDEBUG) std::cerr << " - briggsHeuristic(" << regIdToString(u) << ", " << regIdToString(v) << ") -> " << (briggs_ok ? "OK" : "FAIL") << "\n"; + if (DEEPERDEBUG) std::cerr << " - briggsHeuristic(" << regIdToString(u) << ", " << regIdToString(v) << ") -> " << (briggs_ok ? "OK" : "FAIL") << "\n"; if (briggs_ok) { can_coalesce = true; @@ -549,12 +558,12 @@ void RISCv64RegAlloc::coalesce() { // --- 根据启发式结果进行最终决策 --- if (can_coalesce) { - if (DEEPDEBUG) std::cerr << " -> Heuristic OK. Combining " << regIdToString(v) << " into " << regIdToString(u) << ".\n"; + if (DEEPERDEBUG) std::cerr << " -> Heuristic OK. Combining " << regIdToString(v) << " into " << regIdToString(u) << ".\n"; coalescedMoves.insert(move); combine(u, v); addWorklist(u); } else { - if (DEEPDEBUG) std::cerr << " -> Heuristic failed. Adding to active moves.\n"; + if (DEEPERDEBUG) std::cerr << " -> Heuristic failed. Adding to active moves.\n"; activeMoves.insert(move); } } @@ -563,58 +572,24 @@ void RISCv64RegAlloc::coalesce() { void RISCv64RegAlloc::freeze() { unsigned u = *freezeWorklist.begin(); freezeWorklist.erase(freezeWorklist.begin()); - if (DEEPDEBUG) std::cerr << "[Freeze] Freezing %vreg" << u << " and moving to simplify list.\n"; + if (DEEPERDEBUG) std::cerr << "[Freeze] Freezing %vreg" << u << " and moving to simplify list.\n"; simplifyWorklist.insert(u); freezeMoves(u); } -// // 选择溢出节点 -// // in file: RISCv64RegAlloc.cpp - -// void RISCv64RegAlloc::selectSpill() { -// // [核心逻辑修正] 遵从 George & Appel 论文的“乐观着色”策略。 -// // 此函数不再将节点直接放入 spilledNodes。 -// // 它的作用是选择一个“潜在溢出”节点，并将其移回 simplifyWorklist，以打破僵局。 -// // 真正的溢出决策被推迟到 AssignColors 阶段。 - -// // 使用启发式规则从 spillWorklist 中选择一个节点 m。 -// // 论文建议使用代价函数，这里我们继续使用度数最高的简单启发式。 -// auto it = std::max_element(spillWorklist.begin(), spillWorklist.end(), -// [&](unsigned a, unsigned b){ return degree.at(a) < degree.at(b); }); - -// // 理论上此时 spillWorklist 不应为空，但做保护性检查。 -// if (it == spillWorklist.end()) { -// return; -// } - -// unsigned m = *it; - -// // 1. 将选中的节点 m 从溢出工作列表移动到简化工作列表。 -// spillWorklist.erase(it); -// simplifyWorklist.insert(m); // - -// // 2. 冻结与 m 相关的所有传送指令，因为我们已经放弃了对它的合并尝试。 -// freezeMoves(m); // - -// if (DEEPDEBUG) { -// std::cerr << "[Spill] Optimistically moving %vreg" << m -// << " from spillWorklist to simplifyWorklist.\n"; -// } -// } - // 选择溢出节点 void RISCv64RegAlloc::selectSpill() { auto it = std::max_element(spillWorklist.begin(), spillWorklist.end(), [&](unsigned a, unsigned b){ return degree.at(a) < degree.at(b); }); unsigned m = *it; spillWorklist.erase(it); - if (DEEPDEBUG) std::cerr << "[Spill] Selecting %vreg" << m << " to spill.\n"; + if (DEEPERDEBUG) std::cerr << "[Spill] Selecting %vreg" << m << " to spill.\n"; simplifyWorklist.insert(m); freezeMoves(m); } void RISCv64RegAlloc::assignColors() { - if (DEEPDEBUG) std::cerr << "[AssignColors] Starting...\n"; + if (DEEPERDEBUG) std::cerr << "[AssignColors] Starting...\n"; // 步骤 1: 为 selectStack 中的节点分配颜色 (此部分逻辑不变) while (!selectStack.empty()) { unsigned n = selectStack.back(); @@ -638,12 +613,12 @@ void RISCv64RegAlloc::assignColors() { if (ok_colors.empty()) { spilledNodes.insert(n); - if (DEEPDEBUG) std::cerr << " -> WARNING: No color for %vreg" << n << " from selectStack. Spilling.\n"; + if (DEEPERDEBUG) std::cerr << " -> WARNING: No color for %vreg" << n << " from selectStack. Spilling.\n"; } else { PhysicalReg c = *ok_colors.begin(); coloredNodes.insert(n); color_map[n] = c; - if (DEEPDEBUG) std::cerr << " -> Colored %vreg" << n << " with " << regToString(c) << ".\n"; + if (DEEPERDEBUG) std::cerr << " -> Colored %vreg" << n << " with " << regToString(c) << ".\n"; } } @@ -657,17 +632,17 @@ void RISCv64RegAlloc::assignColors() { if (precolored.count(root_alias)) { const unsigned offset = static_cast(PhysicalReg::PHYS_REG_START_ID); color_map[n] = static_cast(root_alias - offset); - if (DEEPDEBUG) std::cerr << " -> Coalesced %vreg" << n << " gets color from PHYSICAL alias " << regIdToString(root_alias) << ".\n"; + if (DEEPERDEBUG) std::cerr << " -> Coalesced %vreg" << n << " gets color from PHYSICAL alias " << regIdToString(root_alias) << ".\n"; } // 情况 2: 别名是被成功着色的虚拟寄存器 else if (color_map.count(root_alias)) { color_map[n] = color_map.at(root_alias); - if (DEEPDEBUG) std::cerr << " -> Coalesced %vreg" << n << " gets color from VIRTUAL alias " << regIdToString(root_alias) << ".\n"; + if (DEEPERDEBUG) std::cerr << " -> Coalesced %vreg" << n << " gets color from VIRTUAL alias " << regIdToString(root_alias) << ".\n"; } // 情况 3: 别名是被溢出的虚拟寄存器 else { spilledNodes.insert(n); - if (DEEPDEBUG) std::cerr << " -> Alias " << regIdToString(root_alias) << " of %vreg" << n << " was SPILLED. Spilling %vreg" << n << " as well.\n"; + if (DEEPERDEBUG) std::cerr << " -> Alias " << regIdToString(root_alias) << " of %vreg" << n << " was SPILLED. Spilling %vreg" << n << " as well.\n"; } } } @@ -1024,14 +999,14 @@ void RISCv64RegAlloc::addEdge(unsigned u, unsigned v) { RISCv64RegAlloc::VRegSet RISCv64RegAlloc::adjacent(unsigned n) { // 仅在 DEEPDEBUG 模式下启用详细日志 - if (DEEPDEBUG) { + if (DEEPERDEBUG) { // 使用 regIdToString 打印节点 n，无论是物理还是虚拟 std::cerr << "\n[adjacent] >>>>> Executing for node " << regIdToString(n) << " <<<<<\n"; } // 1. 如果节点 n 是物理寄存器，它没有邻接表，直接返回空集 if (precolored.count(n)) { - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[adjacent] Node " << regIdToString(n) << " is precolored. Returning {}.\n"; } return {}; @@ -1039,7 +1014,7 @@ RISCv64RegAlloc::VRegSet RISCv64RegAlloc::adjacent(unsigned n) { // 安全检查：确保 n 在 adjList 中存在，防止 map::at 崩溃 if (adjList.count(n) == 0) { - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[adjacent] WARNING: Node " << regIdToString(n) << " not found in adjList. Returning {}.\n"; } return {}; @@ -1048,7 +1023,7 @@ RISCv64RegAlloc::VRegSet RISCv64RegAlloc::adjacent(unsigned n) { // 2. 获取 n 在冲突图中的所有邻居 VRegSet result = adjList.at(n); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { // 定义一个局部的 lambda 方便打印集合 auto print_set = [this](const VRegSet& s, const std::string& name) { std::cerr << "[adjacent] " << name << " (" << s.size() << "): { "; @@ -1065,11 +1040,11 @@ RISCv64RegAlloc::VRegSet RISCv64RegAlloc::adjacent(unsigned n) { VRegSet removed_from_stack; // 仅用于调试打印 for (auto it = selectStack.rbegin(); it != selectStack.rend(); ++it) { if (result.count(*it)) { - if (DEEPDEBUG) removed_from_stack.insert(*it); + if (DEEPERDEBUG) removed_from_stack.insert(*it); result.erase(*it); } } - if (DEEPDEBUG && !removed_from_stack.empty()) { + if (DEEPERDEBUG && !removed_from_stack.empty()) { std::cerr << "[adjacent] - Removed from selectStack: { "; for(unsigned id : removed_from_stack) std::cerr << regIdToString(id) << " "; std::cerr << "}\n"; @@ -1079,18 +1054,18 @@ RISCv64RegAlloc::VRegSet RISCv64RegAlloc::adjacent(unsigned n) { VRegSet removed_from_coalesced; // 仅用于调试打印 for (unsigned cn : coalescedNodes) { if (result.count(cn)) { - if (DEEPDEBUG) removed_from_coalesced.insert(cn); + if (DEEPERDEBUG) removed_from_coalesced.insert(cn); result.erase(cn); } } - if (DEEPDEBUG && !removed_from_coalesced.empty()) { + if (DEEPERDEBUG && !removed_from_coalesced.empty()) { std::cerr << "[adjacent] - Removed from coalescedNodes: { "; for(unsigned id : removed_from_coalesced) std::cerr << regIdToString(id) << " "; std::cerr << "}\n"; } // 4. 返回最终的、过滤后的“有效”邻居集合 - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[adjacent] >>>>> Returning final adjacent set (" << result.size() << "): { "; for (unsigned id : result) std::cerr << regIdToString(id) << " "; std::cerr << "}\n\n"; @@ -1132,12 +1107,12 @@ void RISCv64RegAlloc::decrementDegree(unsigned m) { enableMoves(nodes_to_enable); spillWorklist.erase(m); if (moveRelated(m)) { - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[decrementDegree] Node " << regIdToString(m) << " has degree " << d << ", now decremented to " << degree.at(m) << ". Added to freezeWorklist.\n"; } freezeWorklist.insert(m); } else { - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[decrementDegree] Node " << regIdToString(m) << " has degree " << d << ", now decremented to " << degree.at(m) << ". Added to simplifyWorklist.\n"; } simplifyWorklist.insert(m); @@ -1176,7 +1151,7 @@ void RISCv64RegAlloc::addWorklist(unsigned u) { if (!moveRelated(u) && degree.at(u) < K) { freezeWorklist.erase(u); simplifyWorklist.insert(u); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[addWorklist] Node " << regIdToString(u) << " added to simplifyWorklist (degree: " << degree.at(u) << ", K: " << K << ").\n"; } } @@ -1184,7 +1159,7 @@ void RISCv64RegAlloc::addWorklist(unsigned u) { // Briggs启发式 bool RISCv64RegAlloc::briggsHeuristic(unsigned u, unsigned v) { - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "\n[Briggs] >>>>> Checking coalesce between " << regIdToString(u) << " and " << regIdToString(v) << " <<<<<\n"; } @@ -1196,7 +1171,7 @@ bool RISCv64RegAlloc::briggsHeuristic(unsigned u, unsigned v) { VRegSet all_adj = u_adj; all_adj.insert(v_adj.begin(), v_adj.end()); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { auto print_set = [this](const VRegSet& s, const std::string& name) { std::cerr << "[Briggs] " << name << " (" << s.size() << "): { "; for (unsigned id : s) std::cerr << regIdToString(id) << " "; @@ -1209,14 +1184,14 @@ bool RISCv64RegAlloc::briggsHeuristic(unsigned u, unsigned v) { // 步骤 3: 遍历合并后的邻居集合，计算度数 >= K 的节点数量 int k = 0; - if (DEEPDEBUG) std::cerr << "[Briggs] Checking significance of combined neighbors:\n"; + if (DEEPERDEBUG) std::cerr << "[Briggs] Checking significance of combined neighbors:\n"; for (unsigned n : all_adj) { // 关键修正：只考虑那些在工作集中的邻居节点 n if (degree.count(n) > 0) { int K = isFPVReg(n) ? K_fp : K_int; if (degree.at(n) >= K) { k++; - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[Briggs] - Node " << regIdToString(n) << " is significant (degree " << degree.at(n) << " >= " << K << "). Count k is now " << k << ".\n"; } } @@ -1227,12 +1202,11 @@ bool RISCv64RegAlloc::briggsHeuristic(unsigned u, unsigned v) { int K_u = isFPVReg(u) ? K_fp : K_int; bool result = (k < K_u); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[Briggs] Final count of significant neighbors (k) = " << k << ".\n"; std::cerr << "[Briggs] K value for node " << regIdToString(u) << " is " << K_u << ".\n"; std::cerr << "[Briggs] >>>>> Result (k < K): " << (result ? "OK (can coalesce)" : "FAIL (cannot coalesce)") << "\n\n"; } - return result; } @@ -1336,7 +1310,7 @@ void RISCv64RegAlloc::freezeMoves(unsigned u) { if (!precolored.count(v_alias) && nodeMoves(v_alias).empty() && degree.at(v_alias) < (isFPVReg(v_alias) ? K_fp : K_int)) { freezeWorklist.erase(v_alias); simplifyWorklist.insert(v_alias); - if (DEEPDEBUG) { + if (DEEPERDEBUG) { std::cerr << "[freezeMoves] Node " << regIdToString(v_alias) << " moved to simplifyWorklist (degree: " << degree.at(v_alias) << ").\n"; } } @@ -1431,9 +1405,26 @@ void RISCv64RegAlloc::dumpState(const std::string& stage) { if (!DEEPDEBUG) return; std::cerr << "\n=============== STATE DUMP (" << stage << ") ===============\n"; auto print_vreg_set = [&](const VRegSet& s, const std::string& name){ - std::cerr << name << " (" << s.size() << "): { "; - for(unsigned v : s) std::cerr << "%vreg" << v << " "; - std::cerr << "}\n"; + if (s.size() > DEBUGLENGTH) { + std::cerr << name << " (" << s.size() << ")\n"; + } + else { + std::cerr << name << " (" << s.size() << "): { "; + for(unsigned v : s) std::cerr << "%vreg" << v << " "; + std::cerr << "}\n"; + } + + }; + auto print_vreg_stack = [&](const VRegStack& s, const std::string& name){ + if (s.size() > DEBUGLENGTH) { + std::cerr << name << " (" << s.size() << ")\n"; + } + else { + std::cerr << name << " (" << s.size() << "): { "; + for(unsigned v : s) std::cerr << "%vreg" << v << " "; + std::cerr << "}\n"; + } + }; print_vreg_set(simplifyWorklist, "SimplifyWorklist"); print_vreg_set(freezeWorklist, "FreezeWorklist"); @@ -1441,9 +1432,7 @@ void RISCv64RegAlloc::dumpState(const std::string& stage) { print_vreg_set(coalescedNodes, "CoalescedNodes"); print_vreg_set(spilledNodes, "SpilledNodes"); - std::cerr << "SelectStack (" << selectStack.size() << "): { "; - for(unsigned v : selectStack) std::cerr << "%vreg" << v << " "; - std::cerr << "}\n"; + print_vreg_stack(selectStack, "SelectStack"); std::cerr << "WorklistMoves (" << worklistMoves.size() << ")\n"; std::cerr << "ActiveMoves (" << activeMoves.size() << ")\n"; diff --git a/src/include/backend/RISCv64/RISCv64RegAlloc.h b/src/include/backend/RISCv64/RISCv64RegAlloc.h index caf8149..bea9ddc 100644 --- a/src/include/backend/RISCv64/RISCv64RegAlloc.h +++ b/src/include/backend/RISCv64/RISCv64RegAlloc.h @@ -1,5 +1,3 @@ -// in file: RISCv64RegAlloc.h - #ifndef RISCV64_REGALLOC_H #define RISCV64_REGALLOC_H @@ -12,6 +10,8 @@ extern int DEBUG; extern int DEEPDEBUG; +extern int DEBUGLENGTH; // 用于限制调试输出的长度 +extern int DEEPERDEBUG; // 用于更深层次的调试输出 namespace sysy { diff --git a/src/sysyc.cpp b/src/sysyc.cpp index 04da485..747eb89 100644 --- a/src/sysyc.cpp +++ b/src/sysyc.cpp @@ -21,6 +21,8 @@ using namespace sysy; int DEBUG = 0; int DEEPDEBUG = 0; +int DEEPERDEBUG = 0; +int DEBUGLENGTH = 50; static string argStopAfter; static string argInputFile;