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[backend]完善了后端流水线

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Lixuanwang
2025-08-05 16:10:04 +08:00
parent 32684d8255
commit 167c2ac2ae
4 changed files with 82 additions and 169 deletions
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46
src/backend/RISCv64/RISCv64LinearScan.cpp
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@@ -643,31 +643,31 @@ void RISCv64LinearScan::applyAllocation() {
}
}
void getInstrUseDef(const MachineInstr* instr, std::set<unsigned>& use, std::set<unsigned>& def) {
auto opcode = instr->getOpcode();
const auto& operands = instr->getOperands();
// void getInstrUseDef(const MachineInstr* instr, std::set<unsigned>& use, std::set<unsigned>& def) {
// auto opcode = instr->getOpcode();
// const auto& operands = instr->getOperands();
auto get_vreg_id_if_virtual = [&](const MachineOperand* op, std::set<unsigned>& s) {
if (op->getKind() == MachineOperand::KIND_REG) {
auto reg_op = static_cast<const RegOperand*>(op);
if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
} else if (op->getKind() == MachineOperand::KIND_MEM) {
auto mem_op = static_cast<const MemOperand*>(op);
auto reg_op = mem_op->getBase();
if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
}
};
// auto get_vreg_id_if_virtual = [&](const MachineOperand* op, std::set<unsigned>& s) {
// if (op->getKind() == MachineOperand::KIND_REG) {
// auto reg_op = static_cast<const RegOperand*>(op);
// if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
// } else if (op->getKind() == MachineOperand::KIND_MEM) {
// auto mem_op = static_cast<const MemOperand*>(op);
// auto reg_op = mem_op->getBase();
// if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
// }
// };
if (op_info.count(opcode)) {
const auto& info = op_info.at(opcode);
for (int idx : info.first) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), def);
for (int idx : info.second) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), use);
for (const auto& op : operands) if (op->getKind() == MachineOperand::KIND_MEM) get_vreg_id_if_virtual(op.get(), use);
} else if (opcode == RVOpcodes::CALL) {
if (!operands.empty() && operands[0]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[0].get(), def);
for (size_t i = 1; i < operands.size(); ++i) if (operands[i]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[i].get(), use);
}
}
// if (op_info.count(opcode)) {
// const auto& info = op_info.at(opcode);
// for (int idx : info.first) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), def);
// for (int idx : info.second) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), use);
// for (const auto& op : operands) if (op->getKind() == MachineOperand::KIND_MEM) get_vreg_id_if_virtual(op.get(), use);
// } else if (opcode == RVOpcodes::CALL) {
// if (!operands.empty() && operands[0]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[0].get(), def);
// for (size_t i = 1; i < operands.size(); ++i) if (operands[i]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[i].get(), use);
// }
// }
bool RISCv64LinearScan::isFPVReg(unsigned vreg) const {
return vreg_type_map.count(vreg) && vreg_type_map.at(vreg)->isFloat();