Default Branch

2d5e248f87 · Merge pull request 'deploy-20250820-3' (#1) from deploy-20250820-3 into master · Updated 2025-08-20 21:20:33 +08:00

Branches

9c5d9ea78c · [optimize]删除多余测试文件 · Updated 2025-08-03 14:38:27 +08:00    gh0s7

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3b1bafde9c · [midend]将alloca声明统一到entry块,增加mem2reg的机会,TODO:不是很明白为什么开了优化过不了一些样例正在排查原因 · Updated 2025-08-03 13:45:13 +08:00    gh0s7

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004ef82488 · [backend-IRC]修复了后端不适配中端全局变量定义的问题 · Updated 2025-08-02 15:10:19 +08:00    gh0s7

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c268191826 · [midend-SCCP]修改BaiscBlock的析构逻辑,将CFG修改的职责交给优化遍,注释Mem2Reg的调试信息。 · Updated 2025-08-01 01:44:33 +08:00    gh0s7

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a5318a2c5c · 为中端加入常量传播Pass · Updated 2025-07-31 20:46:35 +08:00    gh0s7

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fc7afdbb35 · [midend]修复错误的RelExp类型转换 · Updated 2025-07-31 13:55:59 +08:00    gh0s7

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ed8fc32a23 · [deploy]部署版本3 · Updated 2025-07-29 00:48:17 +08:00    gh0s7

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434bcea98e · [PostRA_Scheduler]修复了超大测例卡死的bug · Updated 2025-07-28 23:17:26 +08:00    gh0s7

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792dc9c1f6 · Merge branch 'backend-bss' into backend-rec · Updated 2025-07-28 17:31:23 +08:00    gh0s7

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429e477776 · [backend]引入了对.bss和.data段的区分 · Updated 2025-07-28 17:29:18 +08:00    gh0s7

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ef4bdfc8eb · [deploy]部署版本2 · Updated 2025-07-24 13:30:21 +08:00    gh0s7

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88604c1f94 · [IR]消除Falltrhough现象 · Updated 2025-07-20 18:23:48 +08:00    gh0s7

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c2153b6fab · [deploy]部署版本1 · Updated 2025-07-20 00:10:24 +08:00    gh0s7

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9528335a04 · [backend-llir]修复了许多重构的bug · Updated 2025-07-19 17:50:14 +08:00    gh0s7

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50fd9cffe9 · [IRPrinter&DCE]修改定义方便调试打印,在DEC中增加调试信息 · Updated 2025-07-16 13:04:05 +08:00    gh0s7

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DCE

d9fa9e787a · 删除注释 · Updated 2025-06-25 16:33:43 +08:00    gh0s7

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050113d31d · 增加Reg2Mem,但是会生成死存储指令,需要死代码删除支持识别死存储指令 · Updated 2025-06-25 13:17:16 +08:00    gh0s7

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ac7644f450 · 添加数据流分析类,实现前向后向分析的模板动作,实现活跃变量分析,基本借鉴学长代码,后续可优化实现 · Updated 2025-06-24 23:45:43 +08:00    gh0s7

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b2b88ee511 · [backend-beta] saving for simpler implementation for register allocation · Updated 2025-06-24 05:02:11 +08:00    gh0s7

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10b43fc90d · 修复若干bug · Updated 2025-06-23 17:04:45 +08:00    gh0s7

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