Code Optimization and Clean Up

.gitignore

@@ -8,6 +8,8 @@
 *.code-workspace
 target/*
 .vscode
+test_run_dir
+target
 
 # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 hs_err_pid*

Core.sv

@@ -1,315 +1,427 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
+// Company:
-// Engineer: 
+// Engineer:
-// 
+//
 // Create Date: 2024/12/28 11:25:38
-// Design Name: 
+// Design Name:
 // Module Name: Core
-// Project Name: 
+// Project Name:
-// Target Devices: 
+// Target Devices:
-// Tool Versions: 
+// Tool Versions:
-// Description: 
+// Description:
-// 
+//
-// Dependencies: 
+// Dependencies:
-// 
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module Core(
-        input         clock,
+  input         clock,
-        reset,
+                reset,
-        output [31:0] io_imem_addr,
+  output [31:0] io_imem_addr,
-        input  [31:0] io_imem_inst,
+  input  [31:0] io_imem_inst,
-        output [31:0] io_dmem_addr,
+  output [31:0] io_dmem_addr,
-        input  [31:0] io_dmem_rdata,
+  input  [31:0] io_dmem_rdata,
-        output        io_dmem_wen,
+  output        io_dmem_wen,
-        output [31:0] io_dmem_wdata,
+  output [31:0] io_dmem_wdata,
-        output        io_exit,
+  output [3:0]  io_anodes,
-        output [31:0] s0_value
+  output [6:0]  io_segments,
-    );
+  output        io_exit
+);
 
-    wire [31:0] _regfile_ext_R0_data;
+  wire        exe_jmp_flg;
-    wire [31:0] _regfile_ext_R1_data;
+  wire        exe_br_flg;
-    reg  [31:0] id_reg_pc;
+  wire [31:0] _regfile_ext_R0_data;
-    reg  [31:0] id_reg_inst;
+  wire [31:0] _regfile_ext_R1_data;
-    reg  [31:0] exe_reg_pc;
+  reg  [31:0] id_reg_pc;
-    reg  [4:0]  exe_reg_wb_addr;
+  reg  [31:0] id_reg_inst;
-    reg  [31:0] exe_reg_op1_data;
+  reg  [31:0] exe_reg_pc;
-    reg  [31:0] exe_reg_op2_data;
+  reg  [4:0]  exe_reg_wb_addr;
-    reg  [31:0] exe_reg_rs2_data;
+  reg  [31:0] exe_reg_op1_data;
-    reg  [4:0]  exe_reg_exe_fun;
+  reg  [31:0] exe_reg_op2_data;
-    reg  [1:0]  exe_reg_mem_wen;
+  reg  [31:0] exe_reg_rt_data;
-    reg  [1:0]  exe_reg_rf_wen;
+  reg  [4:0]  exe_reg_exe_fun;
-    reg  [2:0]  exe_reg_wb_sel;
+  reg  [1:0]  exe_reg_mem_wen;
-    reg  [31:0] exe_reg_imm_b_sext;
+  reg  [1:0]  exe_reg_rf_wen;
-    reg  [31:0] mem_reg_pc;
+  reg  [2:0]  exe_reg_wb_sel;
-    reg  [4:0]  mem_reg_wb_addr;
+  reg  [31:0] exe_reg_imm_i_sext;
-    reg  [31:0] mem_reg_alu_out;
+  reg  [31:0] mem_reg_pc;
-    reg  [31:0] mem_reg_rs2_data;
+  reg  [4:0]  mem_reg_wb_addr;
-    reg  [1:0]  mem_reg_rf_wen;
+  reg  [31:0] mem_reg_rt_data;
-    reg  [2:0]  mem_reg_wb_sel;
+  reg  [1:0]  mem_reg_mem_wen;
-    reg  [1:0]  mem_reg_mem_wen;
+  reg  [1:0]  mem_reg_rf_wen;
-    reg  [4:0]  wb_reg_wb_addr;
+  reg  [2:0]  mem_reg_wb_sel;
-    reg  [1:0]  wb_reg_rf_wen;
+  reg  [31:0] mem_reg_alu_out;
-    reg  [31:0] wb_reg_wb_data;
+  reg  [4:0]  wb_reg_wb_addr;
-    reg  [31:0] if_reg_pc;
+  reg  [1:0]  wb_reg_rf_wen;
-    wire        _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
+  reg  [31:0] wb_reg_wb_data;
-    wire        exe_br_flg =
+  reg  [31:0] if_reg_pc;
-                exe_reg_exe_fun == 5'hC
+  wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
-                ? exe_reg_op1_data != exe_reg_op2_data
+  wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
-                : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
+  wire        stall_flg =
-    wire        exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+    _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
-    always @(posedge clock) begin
+    | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
-        automatic logic        _id_inst_T = exe_br_flg | exe_jmp_flg;
+  wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
-        automatic logic        _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
+  wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
-        automatic logic        stall_flg;
+  wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
-        automatic logic [31:0] id_inst;
+  wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
-        automatic logic        _id_rs2_data_T_2;
+  wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
-        automatic logic        _id_rs2_data_T;
+  wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
-        automatic logic [31:0] _id_rs2_data_T_8;
+  wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
-        automatic logic [16:0] _GEN;
+  wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
-        automatic logic        _csignals_T_5;
+  wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
-        automatic logic [19:0] _GEN_0;
+  wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
-        automatic logic        _csignals_T_7;
+  wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
-        automatic logic        _csignals_T_9;
+  wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
-        automatic logic        _csignals_T_11;
+  wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
-        automatic logic        _csignals_T_13;
+  wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
-        automatic logic        _csignals_T_15;
+  wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
-        automatic logic        _csignals_T_17;
+  wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
-        automatic logic        _csignals_T_19;
+  wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
-        automatic logic [16:0] _GEN_1;
+  wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
-        automatic logic        _csignals_T_21;
+  wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
-        automatic logic        _csignals_T_23;
+  wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
-        automatic logic        _csignals_T_25;
+  wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
-        automatic logic        _csignals_T_27;
+  wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
-        automatic logic        _csignals_T_29;
+  wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
-        automatic logic        _csignals_T_31;
+  wire [31:0] exe_alu_out =
-        automatic logic        _csignals_T_33;
+    _exe_alu_out_T
-        automatic logic        _csignals_T_35;
+      ? _exe_alu_out_T_1
-        automatic logic        _csignals_T_37;
+      : _exe_alu_out_T_3
-        automatic logic        _csignals_T_39;
+          ? _exe_alu_out_T_4
-        automatic logic        _GEN_2;
+          : _exe_alu_out_T_6
-        automatic logic        _GEN_3;
+              ? _exe_alu_out_T_7
-        automatic logic [1:0]  csignals_1;
+              : _exe_alu_out_T_8
-        automatic logic [2:0]  _csignals_T_95;
+                  ? _exe_alu_out_T_9
-        automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
+                  : _exe_alu_out_T_10
-        automatic logic [62:0] _exe_alu_out_T_8 =
+                      ? _exe_alu_out_T_11
-                  {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+                      : _exe_alu_out_T_12
-        automatic logic [31:0] exe_alu_out;
+                          ? _exe_alu_out_T_14[31:0]
-        stall_flg =
+                          : _exe_alu_out_T_16
-            _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
+                              ? _exe_alu_out_T_18
-            & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
+                              : _exe_alu_out_T_19
-            & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+                                  ? _exe_alu_out_T_22
-        id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
+                                  : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
-        _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
+  assign exe_br_flg =
-        _id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
+    exe_reg_exe_fun == 5'hB
-        _id_rs2_data_T_8 =
+      ? exe_reg_op1_data == exe_reg_op2_data
-            id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
+      : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
-            ? mem_reg_alu_out
+  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
-            : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
+  wire [31:0] mem_wb_data =
-            ? wb_reg_wb_data
+    mem_reg_wb_sel == 3'h2
-            : _regfile_ext_R0_data;
+      ? io_dmem_rdata
-        _GEN = {id_inst[31:26], id_inst[10:0]};
+      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
-        _csignals_T_5 = _GEN == 17'h20;
+  always @(posedge clock) begin
-        _GEN_0 = {id_inst[31:28], id_inst[15:0]};
+    if (reset) begin
-        _csignals_T_7 = _GEN_0 == 20'h80000;
+      id_reg_pc <= 32'h0;
-        _csignals_T_9 = _GEN == 17'h22;
+      id_reg_inst <= 32'h0;
-        _csignals_T_11 = _GEN == 17'h24;
+      exe_reg_pc <= 32'h0;
-        _csignals_T_13 = _GEN == 17'h25;
+      exe_reg_wb_addr <= 5'h0;
-        _csignals_T_15 = _GEN == 17'h26;
+      exe_reg_op1_data <= 32'h0;
-        _csignals_T_17 = _GEN_0 == 20'hC0000;
+      exe_reg_op2_data <= 32'h0;
-        _csignals_T_19 = _GEN_0 == 20'hD0000;
+      exe_reg_rt_data <= 32'h0;
-        _GEN_1 = {id_inst[30:20], id_inst[5:0]};
+      exe_reg_exe_fun <= 5'h0;
-        _csignals_T_21 = _GEN_1 == 17'h0;
+      exe_reg_mem_wen <= 2'h0;
-        _csignals_T_23 = _GEN_1 == 17'h2;
+      exe_reg_rf_wen <= 2'h0;
-        _csignals_T_25 = _GEN_1 == 17'h3;
+      exe_reg_wb_sel <= 3'h0;
-        _csignals_T_27 = _GEN == 17'h2A;
+      exe_reg_imm_i_sext <= 32'h0;
-        _csignals_T_29 = _GEN_0 == 20'h40000;
+      mem_reg_pc <= 32'h0;
-        _csignals_T_31 = _GEN_0 == 20'h50000;
+      mem_reg_wb_addr <= 5'h0;
-        _csignals_T_33 = id_inst == 32'hC000000;
+      mem_reg_rt_data <= 32'h0;
-        _csignals_T_35 = _GEN_0 == 20'h8;
+      mem_reg_mem_wen <= 2'h0;
-        _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
+      mem_reg_rf_wen <= 2'h0;
-        _csignals_T_39 = id_inst == 32'h0;
+      mem_reg_wb_sel <= 3'h0;
-        _GEN_2 = _csignals_T_29 | _csignals_T_31;
+      mem_reg_alu_out <= 32'h0;
-        _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
+      wb_reg_wb_addr <= 5'h0;
-        csignals_1 =
+      wb_reg_rf_wen <= 2'h0;
-            _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+      wb_reg_wb_data <= 32'h0;
-            | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
+      if_reg_pc <= 32'h0;
-            ? 2'h0
+    end
-            : _csignals_T_33
+    else begin
-            ? 2'h1
+      automatic logic        _id_rt_data_T_5;
-            : _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
+      automatic logic        _id_rt_data_T;
-        _csignals_T_95 =
+      automatic logic        _id_rt_data_T_3;
-            _csignals_T_5
+      automatic logic        _id_rt_data_T_6;
-            ? 3'h1
+      automatic logic        _id_rt_data_T_9;
-            : _csignals_T_7
+      automatic logic [31:0] id_imm_i_sext;
-            ? 3'h2
+      automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
-            : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+      automatic logic        _csignals_T_3;
-            ? 3'h1
+      automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
-            : _csignals_T_17 | _csignals_T_19
+      automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
-            ? 3'h2
+      automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
-            : _GEN_3
+      automatic logic        _csignals_T_9;
-            ? 3'h1
+      automatic logic        _csignals_T_11;
-            : _csignals_T_33
+      automatic logic        _csignals_T_13;
-            ? 3'h4
+      automatic logic        _csignals_T_15;
-            : _csignals_T_35
+      automatic logic        _csignals_T_17;
-            ? 3'h0
+      automatic logic        _csignals_T_19;
-            : _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
+      automatic logic        _csignals_T_21;
-        exe_alu_out =
+      automatic logic        _csignals_T_23;
-            exe_reg_exe_fun == 5'hE
+      automatic logic        _csignals_T_25;
-            ? exe_reg_op1_data
+      automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
-            : exe_reg_exe_fun == 5'h9
+      automatic logic        _csignals_T_27;
-            ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
+      automatic logic        _csignals_T_29;
-            : exe_reg_exe_fun == 5'h8
+      automatic logic        _csignals_T_31;
-            ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
+      automatic logic        _csignals_T_33;
-            : exe_reg_exe_fun == 5'h7
+      automatic logic        _csignals_T_35;
-            ? exe_reg_op1_data >> _GEN_4
+      automatic logic        _GEN_3;
-            : exe_reg_exe_fun == 5'h6
+      automatic logic        _GEN_4;
-            ? _exe_alu_out_T_8[31:0]
+      automatic logic [1:0]  csignals_1;
-            : exe_reg_exe_fun == 5'h5
+      automatic logic [2:0]  csignals_2;
-            ? exe_reg_op1_data ^ exe_reg_op2_data
+      automatic logic        _GEN_5;
-            : exe_reg_exe_fun == 5'h4
+      automatic logic        _GEN_6;
-            ? exe_reg_op1_data | exe_reg_op2_data
+      _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
-            : exe_reg_exe_fun == 5'h3
+      _id_rt_data_T = id_inst[20:16] == 5'h0;
-            ? exe_reg_op1_data & exe_reg_op2_data
+      _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
-            : exe_reg_exe_fun == 5'h2
+      _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
-            ? exe_reg_op1_data - exe_reg_op2_data
+      _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
-            : exe_reg_exe_fun == 5'h1
+      id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
-            ? exe_reg_op1_data + exe_reg_op2_data
+      _csignals_T_3 = id_inst[31:26] == 6'h2B;
-            : 32'h0;
+      _csignals_T_9 = _GEN_1 == 12'h22;
-        if (~stall_flg)
+      _csignals_T_11 = _GEN_1 == 12'h24;
-            id_reg_pc <= if_reg_pc;
+      _csignals_T_13 = _GEN_1 == 12'h25;
-        if (_id_inst_T)
+      _csignals_T_15 = _GEN_1 == 12'h26;
-            id_reg_inst <= 32'h0;
+      _csignals_T_17 = id_inst[31:26] == 6'hC;
-        else if (~stall_flg)
+      _csignals_T_19 = id_inst[31:26] == 6'hD;
-            id_reg_inst <= io_imem_inst;
+      _csignals_T_21 = _GEN_1 == 12'h2A;
-        exe_reg_pc <= id_reg_pc;
+      _csignals_T_23 = id_inst[31:26] == 6'h4;
-        exe_reg_wb_addr <= id_reg_inst[15:11];
+      _csignals_T_25 = id_inst[31:26] == 6'h5;
-        if (csignals_1 == 2'h0)
+      _csignals_T_27 = _GEN_2 == 17'h0;
-            exe_reg_op1_data <=
+      _csignals_T_29 = _GEN_2 == 17'h2;
-                             id_reg_inst[25:21] == 5'h0
+      _csignals_T_31 = _GEN_2 == 17'h3;
-                             ? 32'h0
+      _csignals_T_33 = id_inst[31:26] == 6'h3;
-                             : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
+      _csignals_T_35 = _GEN_1 == 12'h8;
-                             ? mem_reg_alu_out
+      _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
-                             : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
+      _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
-                             ? wb_reg_wb_data
+      csignals_1 =
-                             : _regfile_ext_R1_data;
+        _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
-        else if (csignals_1 == 2'h1)
+        | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
-            exe_reg_op1_data <= id_reg_pc;
+        | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
-        else
+          ? 2'h1
+          : 2'h2;
+      csignals_2 =
+        _csignals_T_1 | _csignals_T_3
+          ? 3'h2
+          : _csignals_T_5
+              ? 3'h1
+              : _csignals_T_7
+                  ? 3'h2
+                  : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                      ? 3'h1
+                      : _csignals_T_17 | _csignals_T_19
+                          ? 3'h2
+                          : _GEN_4
+                              ? 3'h1
+                              : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+      _GEN_5 = _csignals_T_23 | _csignals_T_25;
+      _GEN_6 =
+        _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
+      if (~stall_flg)
+        id_reg_pc <= if_reg_pc;
+      if (_id_inst_T)
+        id_reg_inst <= 32'h20000000;
+      else if (~stall_flg)
+        id_reg_inst <= io_imem_inst;
+      exe_reg_pc <= id_reg_pc;
+      if ((_csignals_T_1
+             ? 3'h2
+             : _csignals_T_3
+                 ? 3'h0
+                 : _GEN_6
+                     ? 3'h1
+                     : _GEN_5
+                         ? 3'h0
+                         : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
+          & id_inst[31:26] == 6'h0)
+        exe_reg_wb_addr <= id_inst[15:11];
+      else if (id_inst[31:26] == 6'h3)
+        exe_reg_wb_addr <= 5'h1F;
+      else
+        exe_reg_wb_addr <= id_inst[20:16];
+      if (csignals_1 == 2'h1) begin
+        if (id_inst[25:21] == 5'h0)
+          exe_reg_op1_data <= 32'h0;
+        else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
+          if (_exe_alu_out_T)
+            exe_reg_op1_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op1_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op1_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op1_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op1_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op1_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op1_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op1_data <= _GEN_0;
+          else if (~_exe_alu_out_T_28)
             exe_reg_op1_data <= 32'h0;
-        if (_csignals_T_95 == 3'h5)
+        end
-            exe_reg_op2_data <= {id_inst[15:0], 16'h0};
+        else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
-        else if (_csignals_T_95 == 3'h4)
+          exe_reg_op1_data <= mem_wb_data;
-            exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
+        else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
-        else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
+          exe_reg_op1_data <= wb_reg_wb_data;
-            exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
-        else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
-            exe_reg_op2_data <= 32'h0;
         else
-            exe_reg_op2_data <= _id_rs2_data_T_8;
+          exe_reg_op1_data <= _regfile_ext_R1_data;
-        exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
+      end
-        if (_csignals_T_5 | _csignals_T_7)
+      else if (csignals_1 == 2'h2)
-            exe_reg_exe_fun <= 5'h1;
+        exe_reg_op1_data <= id_reg_pc;
-        else if (_csignals_T_9)
+      else
-            exe_reg_exe_fun <= 5'h2;
+        exe_reg_op1_data <= 32'h0;
-        else if (_csignals_T_11)
+      if (csignals_2 == 3'h1) begin
-            exe_reg_exe_fun <= 5'h3;
+        if (_id_rt_data_T)
-        else if (_csignals_T_13)
+          exe_reg_op2_data <= 32'h0;
-            exe_reg_exe_fun <= 5'h4;
+        else if (_id_rt_data_T_3) begin
-        else if (_csignals_T_15)
+          if (_exe_alu_out_T)
-            exe_reg_exe_fun <= 5'h5;
+            exe_reg_op2_data <= _exe_alu_out_T_1;
-        else if (_csignals_T_17)
+          else if (_exe_alu_out_T_3)
-            exe_reg_exe_fun <= 5'h3;
+            exe_reg_op2_data <= _exe_alu_out_T_4;
-        else if (_csignals_T_19)
+          else if (_exe_alu_out_T_6)
-            exe_reg_exe_fun <= 5'h4;
+            exe_reg_op2_data <= _exe_alu_out_T_7;
-        else if (_csignals_T_21)
+          else if (_exe_alu_out_T_8)
-            exe_reg_exe_fun <= 5'h6;
+            exe_reg_op2_data <= _exe_alu_out_T_9;
-        else if (_csignals_T_23)
+          else if (_exe_alu_out_T_10)
-            exe_reg_exe_fun <= 5'h7;
+            exe_reg_op2_data <= _exe_alu_out_T_11;
-        else if (_csignals_T_25)
+          else if (_exe_alu_out_T_12)
-            exe_reg_exe_fun <= 5'h8;
+            exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
-        else if (_csignals_T_27)
+          else if (_exe_alu_out_T_16)
-            exe_reg_exe_fun <= 5'h9;
+            exe_reg_op2_data <= _exe_alu_out_T_18;
-        else if (_csignals_T_29)
+          else if (_exe_alu_out_T_19)
-            exe_reg_exe_fun <= 5'hB;
+            exe_reg_op2_data <= _exe_alu_out_T_22;
-        else if (_csignals_T_31)
+          else if (_exe_alu_out_T_24)
-            exe_reg_exe_fun <= 5'hC;
+            exe_reg_op2_data <= _GEN_0;
+          else
+            exe_reg_op2_data <= _exe_alu_out_T_29;
+        end
+        else if (_id_rt_data_T_6)
+          exe_reg_op2_data <= mem_wb_data;
+        else if (_id_rt_data_T_9)
+          exe_reg_op2_data <= wb_reg_wb_data;
+        else
+          exe_reg_op2_data <= _regfile_ext_R0_data;
+      end
+      else if (csignals_2 == 3'h2)
+        exe_reg_op2_data <= id_imm_i_sext;
+      else if (csignals_2 == 3'h4)
+        exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
+      else
+        exe_reg_op2_data <= 32'h0;
+      exe_reg_rt_data <=
+        _id_rt_data_T
+          ? 32'h0
+          : _id_rt_data_T_3
+              ? exe_alu_out
+              : _id_rt_data_T_6
+                  ? mem_wb_data
+                  : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
+      if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_9)
+        exe_reg_exe_fun <= 5'h2;
+      else if (_csignals_T_11)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_13)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_15)
+        exe_reg_exe_fun <= 5'h5;
+      else if (_csignals_T_17)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_19)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_21)
+        exe_reg_exe_fun <= 5'h9;
+      else if (_csignals_T_23)
+        exe_reg_exe_fun <= 5'hB;
+      else if (_csignals_T_25)
+        exe_reg_exe_fun <= 5'hC;
+      else if (_csignals_T_27)
+        exe_reg_exe_fun <= 5'h6;
+      else if (_csignals_T_29)
+        exe_reg_exe_fun <= 5'h7;
+      else if (_csignals_T_31)
+        exe_reg_exe_fun <= 5'h8;
+      else if (_csignals_T_33)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_35)
+        exe_reg_exe_fun <= 5'hD;
+      else
+        exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
+      if (_csignals_T_1) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h2;
+      end
+      else if (_csignals_T_3) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else if (_GEN_6) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h1;
+      end
+      else if (_GEN_5) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else begin
+        exe_reg_rf_wen <=
+          {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
+        if (_GEN_3)
+          exe_reg_wb_sel <= 3'h1;
         else if (_csignals_T_33)
-            exe_reg_exe_fun <= 5'h1;
+          exe_reg_wb_sel <= 3'h3;
-        else if (_csignals_T_35)
-            exe_reg_exe_fun <= 5'hE;
         else
-            exe_reg_exe_fun <= {4'h0, _csignals_T_37};
+          exe_reg_wb_sel <= 3'h0;
-        exe_reg_mem_wen <= 2'h0;
+      end
-        if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+      exe_reg_imm_i_sext <= id_imm_i_sext;
-                | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
+      mem_reg_pc <= exe_reg_pc;
-                | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
+      mem_reg_wb_addr <= exe_reg_wb_addr;
-            exe_reg_rf_wen <= 2'h1;
+      mem_reg_rt_data <= exe_reg_rt_data;
-            exe_reg_wb_sel <= 3'h1;
+      mem_reg_mem_wen <= exe_reg_mem_wen;
-        end
+      mem_reg_rf_wen <= exe_reg_rf_wen;
-        else if (_GEN_2) begin
+      mem_reg_wb_sel <= exe_reg_wb_sel;
-            exe_reg_rf_wen <= 2'h0;
+      mem_reg_alu_out <= exe_alu_out;
-            exe_reg_wb_sel <= 3'h0;
+      wb_reg_wb_addr <= mem_reg_wb_addr;
-        end
+      wb_reg_rf_wen <= mem_reg_rf_wen;
-        else if (_csignals_T_33) begin
+      wb_reg_wb_data <= mem_wb_data;
-            exe_reg_rf_wen <= 2'h1;
+      if (exe_br_flg)
-            exe_reg_wb_sel <= 3'h3;
+        if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
-        end
+      else if (exe_jmp_flg)
-        else if (_csignals_T_35) begin
+        if_reg_pc <= exe_alu_out;
-            exe_reg_rf_wen <= 2'h0;
+      else if (~stall_flg)
-            exe_reg_wb_sel <= 3'h0;
+        if_reg_pc <= if_reg_pc + 32'h4;
-        end
+    end
-        else begin
+  end // always @(posedge)
-            exe_reg_rf_wen <= {1'h0, _csignals_T_37};
+  regfile_32x32 regfile_ext (
-            exe_reg_wb_sel <= {2'h0, _csignals_T_37};
+    .R0_addr (id_inst[20:16]),
-        end
+    .R0_en   (1'h1),
-        exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
+    .R0_clk  (clock),
-        mem_reg_pc <= exe_reg_pc;
+    .R0_data (_regfile_ext_R0_data),
-        mem_reg_wb_addr <= exe_reg_wb_addr;
+    .R1_addr (id_inst[25:21]),
-        mem_reg_alu_out <= exe_alu_out;
+    .R1_en   (1'h1),
-        mem_reg_rs2_data <= exe_reg_rs2_data;
+    .R1_clk  (clock),
-        mem_reg_rf_wen <= exe_reg_rf_wen;
+    .R1_data (_regfile_ext_R1_data),
-        mem_reg_wb_sel <= exe_reg_wb_sel;
+    .W0_addr (wb_reg_wb_addr),
-        mem_reg_mem_wen <= exe_reg_mem_wen;
+    .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
-        wb_reg_wb_addr <= mem_reg_wb_addr;
+    .W0_clk  (clock),
-        wb_reg_rf_wen <= mem_reg_rf_wen;
+    .io_anodes (io_anodes),
-        wb_reg_wb_data <=
+    .io_segments (io_segments),
-                       mem_reg_wb_sel == 3'h3
+    .W0_data (wb_reg_wb_data)
-                       ? mem_reg_pc + 32'h4
+  );
-                       : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
+  assign io_imem_addr = if_reg_pc;
-        if (reset)
+  assign io_dmem_addr = mem_reg_alu_out;
-            if_reg_pc <= 32'h0;
+  assign io_dmem_wen = mem_reg_mem_wen[0];
-        else if (exe_br_flg)
+  assign io_dmem_wdata = mem_reg_rt_data;
-            if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
+  assign io_exit = id_reg_inst == 32'h114514;
-        else if (exe_jmp_flg)
+endmodule
-            if_reg_pc <= exe_alu_out;
-        else if (~stall_flg)
-            if_reg_pc <= if_reg_pc + 32'h4;
-    end // always @(posedge)
-    regfile_32x32 regfile_ext (
-                      .R0_addr (id_reg_inst[20:16]),
-                      .R0_en   (1'h1),
-                      .R0_clk  (clock),
-                      .R0_data (_regfile_ext_R0_data),
-                      .R1_addr (id_reg_inst[25:21]),
-                      .R1_en   (1'h1),
-                      .R1_clk  (clock),
-                      .R1_data (_regfile_ext_R1_data),
-                      .W0_addr (wb_reg_wb_addr),
-                      .W0_en   (_id_rs2_data_T_5),
-                      .W0_clk  (clock),
-                      .W0_data (wb_reg_wb_data)
-                  );
-    assign io_imem_addr = if_reg_pc;
-    assign io_dmem_addr = mem_reg_alu_out;
-    assign io_dmem_wen = mem_reg_mem_wen[0];
-    assign io_dmem_wdata = mem_reg_rs2_data;
-    assign io_exit = id_reg_inst == 32'h00000000;
-    assign s0_value = _regfile_ext_R0_data;
-endmodule

Memory.sv

@@ -1,88 +1,60 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
+// Company:
-// Engineer: 
+// Engineer:
-// 
+//
 // Create Date: 2024/12/28 11:28:52
-// Design Name: 
+// Design Name:
 // Module Name: Regfile
-// Project Name: 
+// Project Name:
-// Target Devices: 
+// Target Devices:
-// Tool Versions: 
+// Tool Versions:
-// Description: 
+// Description:
-// 
+//
-// Dependencies: 
+// Dependencies:
-// 
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
-
+// VCS coverage exclude_file
-module mem_512x32(
-        input  [8:0]  R0_addr,
-        input         R0_en,
-        R0_clk,
-        output [31:0] R0_data,
-        input  [8:0]  R1_addr,
-        input         R1_en,
-        R1_clk,
-        output [31:0] R1_data,
-        input  [8:0]  W0_addr,
-        input         W0_en,
-        W0_clk,
-        input  [31:0] W0_data
-    );
-
-    reg [31:0] Memory[0:511];
-    reg        _R0_en_d0;
-    reg [8:0]  _R0_addr_d0;
-    always @(posedge R0_clk) begin
-        _R0_en_d0 <= R0_en;
-        _R0_addr_d0 <= R0_addr;
-    end // always @(posedge)
-    reg        _R1_en_d0;
-    reg [8:0]  _R1_addr_d0;
-    always @(posedge R1_clk) begin
-        _R1_en_d0 <= R1_en;
-        _R1_addr_d0 <= R1_addr;
-    end // always @(posedge)
-    always @(posedge W0_clk) begin
-        if (W0_en & 1'h1)
-            Memory[W0_addr] <= W0_data;
-    end // always @(posedge)
-`ifdef ENABLE_INITIAL_MEM_
-    initial
-        $readmemh("src/hex/mem.hex", Memory);
-`endif // ENABLE_INITIAL_MEM_
-
-    assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
-    assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
-endmodule
-
 module Memory(
-        input         clock,
+  input         clock,
-        input  [31:0] io_imem_addr,
+  input  [31:0] io_imem_addr,
-        output [31:0] io_imem_inst,
+  output [31:0] io_imem_inst,
-        input  [31:0] io_dmem_addr,
+  input  [31:0] io_dmem_addr,
-        output [31:0] io_dmem_rdata,
+  output [31:0] io_dmem_rdata,
-        input         io_dmem_wen,
+  input         io_dmem_wen,
-        input  [31:0] io_dmem_wdata
+  input  [31:0] io_dmem_wdata
-    );
+);
 
-    mem_512x32 mem_ext (
+
-                   .R0_addr (io_imem_addr[10:2]),
+  reg [31:0] mem [0:63];
-                   .R0_en   (1'h1),
+
-                   .R0_clk  (clock),
+
-                   .R0_data (io_imem_inst),
+  initial begin
-                   .R1_addr (io_dmem_addr[10:2]),
+    mem[0] = 32'h20080001;  // addi $t0, $zero, 1
-                   .R1_en   (1'h1),
+    mem[1] = 32'h20100000;  // addi $s0, $zero, 0
-                   .R1_clk  (clock),
+    mem[2] = 32'h20120065;  // addi $s2, $zero, 101
-                   .R1_data (io_dmem_rdata),
+    mem[3] = 32'h02088020;  // add $s0, $s0, $t0
-                   .W0_addr (io_dmem_addr[10:2]),
+    mem[4] = 32'h21080001;  // addi $t0, $t0, 1
-                   .W0_en   (io_dmem_wen),
+    mem[5] = 32'h0112502a;  // slt $t2, $t0, $s2
-                   .W0_clk  (clock),
+    mem[6] = 32'h1540fffc;  // bne $t2, $zero, -4
-                   .W0_data (io_dmem_wdata)
+    mem[7] = 32'h00000000;  // nop
-               );
+    mem[8] = 32'h00114514;  // exit
-endmodule
+  end
+
+
+  assign io_imem_inst = mem[io_imem_addr[7:2]];
+
+  assign io_dmem_rdata = mem[io_dmem_addr[7:2]];
+
+
+  always @(posedge clock) begin
+    if (io_dmem_wen) begin
+      mem[io_dmem_addr[7:2]] <= io_dmem_wdata;
+    end
+  end
+endmodule

Regfile.sv

@@ -1,58 +1,54 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
+// Company:
-// Engineer: 
+// Engineer:
-// 
+//
 // Create Date: 2024/12/28 11:28:52
-// Design Name: 
+// Design Name:
 // Module Name: Regfile
-// Project Name: 
+// Project Name:
-// Target Devices: 
+// Target Devices:
-// Tool Versions: 
+// Tool Versions:
-// Description: 
+// Description:
-// 
+//
-// Dependencies: 
+// Dependencies:
-// 
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module regfile_32x32(
-        input  [4:0]  R0_addr,
+  input  [4:0]  R0_addr,
-        input         R0_en,
+  input         R0_en,
-        R0_clk,
+                R0_clk,
-        output [31:0] R0_data,
+  output [31:0] R0_data,
-        input  [4:0]  R1_addr,
+  input  [4:0]  R1_addr,
-        input         R1_en,
+  input         R1_en,
-        R1_clk,
+                R1_clk,
-        output [31:0] R1_data,
+  output [31:0] R1_data,
-        input  [4:0]  W0_addr,
+  input  [4:0]  W0_addr,
-        input         W0_en,
+  input         W0_en,
-        W0_clk,
+                W0_clk,
-        input  [31:0] W0_data
+  output [3:0]  io_anodes,
-    );
+  output [6:0]  io_segments,
-
+  input  [31:0] W0_data
-    reg [31:0] Memory[0:31];
+);
-    reg        _R0_en_d0;
-    reg [4:0]  _R0_addr_d0;
-    always @(posedge R0_clk) begin
-        _R0_en_d0 <= R0_en;
-        _R0_addr_d0 <= R0_addr;
-    end // always @(posedge)
-    reg        _R1_en_d0;
-    reg [4:0]  _R1_addr_d0;
-    always @(posedge R1_clk) begin
-        _R1_en_d0 <= R1_en;
-        _R1_addr_d0 <= R1_addr;
-    end // always @(posedge)
-    always @(posedge W0_clk) begin
-        if (W0_en & 1'h1)
-            Memory[W0_addr] <= W0_data;
-    end // always @(posedge)
-    assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
-    assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
 
+  reg [31:0] Memory[0:31];
+  always @(posedge W0_clk) begin
+    if (W0_en & 1'h1)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
+  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
+  wire [31:0] reg16_value = Memory[16];
+  DynamicDisplay display (
+                       .clock        (W0_clk),
+                       .reset        (1'b0),
+                       .reg_result   (reg16_value),
+                       .io_anodes    (io_anodes),
+                       .io_segments  (io_segments)
+                   );
 endmodule

Top.sv

@@ -1,68 +1,58 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
+// Company:
-// Engineer: 
+// Engineer:
-// 
+//
 // Create Date: 2024/12/28 11:25:38
-// Design Name: 
+// Design Name:
 // Module Name: Core
-// Project Name: 
+// Project Name:
-// Target Devices: 
+// Target Devices:
-// Tool Versions: 
+// Tool Versions:
-// Description: 
+// Description:
-// 
+//
-// Dependencies: 
+// Dependencies:
-// 
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module Top(
-        input  clock,
+  input  clock,
-        reset,
+         reset,
-        output io_exit,
+  output [3:0]  io_anodes,
-        output [3:0] io_anodes,    // 新增：七段显示器的阳极控制信号
+  output [6:0]  io_segments,
-        output [6:0] io_segments   // 新增：七段显示器的段控制信号
+  output io_exit
-    );
+);
-
-    wire [31:0] _memory_io_imem_inst;
-    wire [31:0] _memory_io_dmem_rdata;
-    wire [31:0] _core_io_imem_addr;
-    wire [31:0] _core_io_dmem_addr;
-    wire        _core_io_dmem_wen;
-    wire [31:0] _core_io_dmem_wdata;
-    wire [31:0] _core_s0_value;
-    Core core (
-             .clock         (clock),
-             .reset         (reset),
-             .io_imem_addr  (_core_io_imem_addr),
-             .io_imem_inst  (_memory_io_imem_inst),
-             .io_dmem_addr  (_core_io_dmem_addr),
-             .io_dmem_rdata (_memory_io_dmem_rdata),
-             .io_dmem_wen   (_core_io_dmem_wen),
-             .io_dmem_wdata (_core_io_dmem_wdata),
-             .io_exit       (io_exit),
-             .s0_value      (_core_s0_value)
-         );
-    Memory memory (
-               .clock         (clock),
-               .io_imem_addr  (_core_io_imem_addr),
-               .io_imem_inst  (_memory_io_imem_inst),
-               .io_dmem_addr  (_core_io_dmem_addr),
-               .io_dmem_rdata (_memory_io_dmem_rdata),
-               .io_dmem_wen   (_core_io_dmem_wen),
-               .io_dmem_wdata (_core_io_dmem_wdata)
-           );
-        // 实例化 DynamicDisplay 模块
-    DynamicDisplay display (
-        .clock      (clock),
-        .reset      (reset),
-        .reg_result (_core_s0_value), // 连接 $s0 的值
-        .io_anodes  (io_anodes),      // 连接七段显示器的阳极控制信号
-        .io_segments(io_segments)     // 连接七段显示器的段控制信号
-    );
-endmodule
 
+  wire [31:0] _memory_io_imem_inst;
+  wire [31:0] _memory_io_dmem_rdata;
+  wire [31:0] _core_io_imem_addr;
+  wire [31:0] _core_io_dmem_addr;
+  wire        _core_io_dmem_wen;
+  wire [31:0] _core_io_dmem_wdata;
+  Core core (
+    .clock         (clock),
+    .reset         (reset),
+    .io_imem_addr  (_core_io_imem_addr),
+    .io_imem_inst  (_memory_io_imem_inst),
+    .io_dmem_addr  (_core_io_dmem_addr),
+    .io_dmem_rdata (_memory_io_dmem_rdata),
+    .io_dmem_wen   (_core_io_dmem_wen),
+    .io_dmem_wdata (_core_io_dmem_wdata),
+    .io_anodes     (io_anodes),
+    .io_segments   (io_segments),
+    .io_exit       (io_exit)
+  );
+  Memory memory (
+    .clock         (clock),
+    .io_imem_addr  (_core_io_imem_addr),
+    .io_imem_inst  (_memory_io_imem_inst),
+    .io_dmem_addr  (_core_io_dmem_addr),
+    .io_dmem_rdata (_memory_io_dmem_rdata),
+    .io_dmem_wen   (_core_io_dmem_wen),
+    .io_dmem_wdata (_core_io_dmem_wdata)
+  );
+endmodule

TopOrigin.sv

@@ -1,15 +1,4 @@
 // Generated by CIRCT firtool-1.62.0
-// Standard header to adapt well known macros for prints and assertions.
-
-// Users can define 'PRINTF_COND' to add an extra gate to prints.
-`ifndef PRINTF_COND_
-  `ifdef PRINTF_COND
-    `define PRINTF_COND_ (`PRINTF_COND)
-  `else  // PRINTF_COND
-    `define PRINTF_COND_ 1
-  `endif // PRINTF_COND
-`endif // not def PRINTF_COND_
-
 // VCS coverage exclude_file
 module regfile_32x32(
   input  [4:0]  R0_addr,
@@ -47,316 +36,424 @@ module Core(
   output        io_exit
 );
 
+  wire        exe_jmp_flg;
+  wire        exe_br_flg;
   wire [31:0] _regfile_ext_R0_data;
   wire [31:0] _regfile_ext_R1_data;
-  reg  [31:0] pc_reg;
+  reg  [31:0] id_reg_pc;
-  wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
+  reg  [31:0] id_reg_inst;
-  wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]};
+  reg  [31:0] exe_reg_pc;
-  wire        jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8;
+  reg  [4:0]  exe_reg_wb_addr;
-  wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0;
+  reg  [31:0] exe_reg_op1_data;
-  wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0;
+  reg  [31:0] exe_reg_op2_data;
-  wire        _csignals_T_1 = io_imem_inst[31:26] == 6'h23;
+  reg  [31:0] exe_reg_rt_data;
-  wire        _csignals_T_3 = io_imem_inst[31:26] == 6'h2B;
+  reg  [4:0]  exe_reg_exe_fun;
-  wire        _csignals_T_5 = _GEN == 12'h20;
+  reg  [1:0]  exe_reg_mem_wen;
-  wire        _csignals_T_7 = io_imem_inst[31:26] == 6'h8;
+  reg  [1:0]  exe_reg_rf_wen;
-  wire        _csignals_T_9 = _GEN == 12'h22;
+  reg  [2:0]  exe_reg_wb_sel;
-  wire        _csignals_T_11 = _GEN == 12'h24;
+  reg  [31:0] exe_reg_imm_i_sext;
-  wire        _csignals_T_13 = _GEN == 12'h25;
+  reg  [31:0] mem_reg_pc;
-  wire        _csignals_T_15 = _GEN == 12'h26;
+  reg  [4:0]  mem_reg_wb_addr;
-  wire        _csignals_T_17 = io_imem_inst[31:26] == 6'hC;
+  reg  [31:0] mem_reg_rt_data;
-  wire        _csignals_T_19 = io_imem_inst[31:26] == 6'hD;
+  reg  [1:0]  mem_reg_mem_wen;
-  wire        _csignals_T_21 = _GEN == 12'h2A;
+  reg  [1:0]  mem_reg_rf_wen;
-  wire        _csignals_T_23 = io_imem_inst[31:26] == 6'h4;
+  reg  [2:0]  mem_reg_wb_sel;
-  wire        _csignals_T_25 = io_imem_inst[31:26] == 6'h5;
+  reg  [31:0] mem_reg_alu_out;
-  wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]};
+  reg  [4:0]  wb_reg_wb_addr;
-  wire        _csignals_T_27 = _GEN_0 == 17'h0;
+  reg  [1:0]  wb_reg_rf_wen;
-  wire        _csignals_T_29 = _GEN_0 == 17'h2;
+  reg  [31:0] wb_reg_wb_data;
-  wire        _csignals_T_31 = _GEN_0 == 17'h3;
+  reg  [31:0] if_reg_pc;
-  wire        _csignals_T_33 = io_imem_inst[31:26] == 6'h3;
+  wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
-  wire        _csignals_T_35 = _GEN == 12'h8;
+  wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
-  wire [4:0]  csignals_0 =
+  wire        stall_flg =
-    _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7
+    _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
-      ? 5'h1
+    | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
-      : _csignals_T_9
+  wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
-          ? 5'h2
+  wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
-          : _csignals_T_11
+  wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
-              ? 5'h3
+  wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
-              : _csignals_T_13
+  wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
-                  ? 5'h4
+  wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
-                  : _csignals_T_15
+  wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
-                      ? 5'h5
+  wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
-                      : _csignals_T_17
+  wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
-                          ? 5'h3
+  wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
-                          : _csignals_T_19
+  wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
-                              ? 5'h4
+  wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
-                              : _csignals_T_21
+  wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
-                                  ? 5'h9
+  wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
-                                  : _csignals_T_23
+  wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
-                                      ? 5'hB
+  wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
-                                      : _csignals_T_25
+  wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
-                                          ? 5'hC
+  wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
-                                          : _csignals_T_27
+  wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
-                                              ? 5'h6
+  wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
-                                              : _csignals_T_29
+  wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
-                                                  ? 5'h7
+  wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
-                                                  : _csignals_T_31
+  wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
-                                                      ? 5'h8
+  wire [31:0] exe_alu_out =
-                                                      : _csignals_T_33
+    _exe_alu_out_T
-                                                          ? 5'h1
+      ? _exe_alu_out_T_1
-                                                          : _csignals_T_35 ? 5'hD : 5'h0;
+      : _exe_alu_out_T_3
-  wire        _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
+          ? _exe_alu_out_T_4
-  wire        _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1;
+          : _exe_alu_out_T_6
-  wire [1:0]  csignals_1 =
+              ? _exe_alu_out_T_7
-    _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
+              : _exe_alu_out_T_8
-    | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19
+                  ? _exe_alu_out_T_9
-    | _GEN_2 | ~_csignals_T_33
+                  : _exe_alu_out_T_10
-      ? 2'h1
+                      ? _exe_alu_out_T_11
-      : 2'h2;
+                      : _exe_alu_out_T_12
-  wire [2:0]  csignals_2 =
+                          ? _exe_alu_out_T_14[31:0]
-    _csignals_T_1 | _csignals_T_3
+                          : _exe_alu_out_T_16
-      ? 3'h2
+                              ? _exe_alu_out_T_18
-      : _csignals_T_5
+                              : _exe_alu_out_T_19
-          ? 3'h1
+                                  ? _exe_alu_out_T_22
-          : _csignals_T_7
+                                  : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
-              ? 3'h2
+  assign exe_br_flg =
-              : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+    exe_reg_exe_fun == 5'hB
-                  ? 3'h1
+      ? exe_reg_op1_data == exe_reg_op2_data
-                  : _csignals_T_17 | _csignals_T_19
+      : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
-                      ? 3'h2
+  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
-                      : _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+  wire [31:0] mem_wb_data =
-  wire        _GEN_3 = _csignals_T_23 | _csignals_T_25;
+    mem_reg_wb_sel == 3'h2
-  wire        _GEN_4 =
+      ? io_dmem_rdata
-    _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
-    | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
-  wire [1:0]  csignals_4 =
-    _csignals_T_1
-      ? 2'h1
-      : _csignals_T_3
-          ? 2'h0
-          : _GEN_4
-              ? 2'h1
-              : _GEN_3
-                  ? 2'h0
-                  : {1'h0,
-                     _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
-  wire [2:0]  csignals_5 =
-    _csignals_T_1
-      ? 3'h2
-      : _csignals_T_3
-          ? 3'h0
-          : _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0;
-  wire        _op1_data_T = csignals_1 == 2'h1;
-  wire        _op1_data_T_1 = csignals_1 == 2'h2;
-  wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
-  wire [31:0] op2_data =
-    csignals_2 == 3'h1
-      ? rt_data
-      : csignals_2 == 3'h2
-          ? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
-          : csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
-  wire        _alu_out_T = csignals_0 == 5'h1;
-  wire [31:0] _alu_out_T_1 = op1_data + op2_data;
-  wire        _alu_out_T_3 = csignals_0 == 5'h2;
-  wire [31:0] _alu_out_T_4 = op1_data - op2_data;
-  wire        _alu_out_T_6 = csignals_0 == 5'h3;
-  wire [31:0] _alu_out_T_7 = op1_data & op2_data;
-  wire        _alu_out_T_8 = csignals_0 == 5'h4;
-  wire [31:0] _alu_out_T_9 = op1_data | op2_data;
-  wire        _alu_out_T_10 = csignals_0 == 5'h5;
-  wire [31:0] _alu_out_T_11 = op1_data ^ op2_data;
-  wire        _alu_out_T_12 = csignals_0 == 5'h6;
-  wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
-  wire        _alu_out_T_16 = csignals_0 == 5'h7;
-  wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]};
-  wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5;
-  wire        _alu_out_T_19 = csignals_0 == 5'h8;
-  wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5);
-  wire        _alu_out_T_24 = csignals_0 == 5'h9;
-  wire        _alu_out_T_28 = csignals_0 == 5'hD;
-  wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)};
-  wire [31:0] alu_out =
-    _alu_out_T
-      ? _alu_out_T_1
-      : _alu_out_T_3
-          ? _alu_out_T_4
-          : _alu_out_T_6
-              ? _alu_out_T_7
-              : _alu_out_T_8
-                  ? _alu_out_T_9
-                  : _alu_out_T_10
-                      ? _alu_out_T_11
-                      : _alu_out_T_12
-                          ? _alu_out_T_14[31:0]
-                          : _alu_out_T_16
-                              ? _alu_out_T_18
-                              : _alu_out_T_19
-                                  ? _alu_out_T_22
-                                  : _alu_out_T_24
-                                      ? _GEN_6
-                                      : _alu_out_T_28 ? op1_data : 32'h0;
-  wire        _br_flg_T_3 = op1_data == op2_data;
-  wire        br_flg =
-    csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
-  wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
-  wire [31:0] wb_data =
-    csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out;
-  wire [4:0]  wb_addr =
-    csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0
-      ? io_imem_inst[15:11]
-      : io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16];
-  `ifndef SYNTHESIS
-    always @(posedge clock) begin
-      if ((`PRINTF_COND_) & ~reset) begin
-        $fwrite(32'h80000002, "---------------\n");
-        $fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst);
-        $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst);
-        $fwrite(32'h80000002, "pc_next: 0x%x\n",
-                br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
-        $fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0);
-        $fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
-        $fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]);
-        $fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
-        $fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data);
-        $fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4);
-        $fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
-        $fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data);
-        $fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
-        $fwrite(32'h80000002, "---------------\n");
-      end
-    end // always @(posedge)
-  `endif // not def SYNTHESIS
   always @(posedge clock) begin
-    if (reset)
+    if (reset) begin
-      pc_reg <= 32'h0;
+      id_reg_pc <= 32'h0;
-    else if (br_flg)
+      id_reg_inst <= 32'h0;
-      pc_reg <= br_target;
+      exe_reg_pc <= 32'h0;
-    else if (jmp_flg) begin
+      exe_reg_wb_addr <= 5'h0;
-      if (_alu_out_T)
+      exe_reg_op1_data <= 32'h0;
-        pc_reg <= _alu_out_T_1;
+      exe_reg_op2_data <= 32'h0;
-      else if (_alu_out_T_3)
+      exe_reg_rt_data <= 32'h0;
-        pc_reg <= _alu_out_T_4;
+      exe_reg_exe_fun <= 5'h0;
-      else if (_alu_out_T_6)
+      exe_reg_mem_wen <= 2'h0;
-        pc_reg <= _alu_out_T_7;
+      exe_reg_rf_wen <= 2'h0;
-      else if (_alu_out_T_8)
+      exe_reg_wb_sel <= 3'h0;
-        pc_reg <= _alu_out_T_9;
+      exe_reg_imm_i_sext <= 32'h0;
-      else if (_alu_out_T_10)
+      mem_reg_pc <= 32'h0;
-        pc_reg <= _alu_out_T_11;
+      mem_reg_wb_addr <= 5'h0;
-      else if (_alu_out_T_12)
+      mem_reg_rt_data <= 32'h0;
-        pc_reg <= _alu_out_T_14[31:0];
+      mem_reg_mem_wen <= 2'h0;
-      else if (_alu_out_T_16)
+      mem_reg_rf_wen <= 2'h0;
-        pc_reg <= _alu_out_T_18;
+      mem_reg_wb_sel <= 3'h0;
-      else if (_alu_out_T_19)
+      mem_reg_alu_out <= 32'h0;
-        pc_reg <= _alu_out_T_22;
+      wb_reg_wb_addr <= 5'h0;
-      else if (_alu_out_T_24)
+      wb_reg_rf_wen <= 2'h0;
-        pc_reg <= _GEN_6;
+      wb_reg_wb_data <= 32'h0;
-      else if (_alu_out_T_28) begin
+      if_reg_pc <= 32'h0;
-        if (_op1_data_T)
+    end
-          pc_reg <= rs_data;
+    else begin
-        else if (~_op1_data_T_1)
+      automatic logic        _id_rt_data_T_5;
-          pc_reg <= 32'h0;
+      automatic logic        _id_rt_data_T;
-      end
+      automatic logic        _id_rt_data_T_3;
-      else
+      automatic logic        _id_rt_data_T_6;
-        pc_reg <= 32'h0;
+      automatic logic        _id_rt_data_T_9;
+      automatic logic [31:0] id_imm_i_sext;
+      automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
+      automatic logic        _csignals_T_3;
+      automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
+      automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
+      automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
+      automatic logic        _csignals_T_9;
+      automatic logic        _csignals_T_11;
+      automatic logic        _csignals_T_13;
+      automatic logic        _csignals_T_15;
+      automatic logic        _csignals_T_17;
+      automatic logic        _csignals_T_19;
+      automatic logic        _csignals_T_21;
+      automatic logic        _csignals_T_23;
+      automatic logic        _csignals_T_25;
+      automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
+      automatic logic        _csignals_T_27;
+      automatic logic        _csignals_T_29;
+      automatic logic        _csignals_T_31;
+      automatic logic        _csignals_T_33;
+      automatic logic        _csignals_T_35;
+      automatic logic        _GEN_3;
+      automatic logic        _GEN_4;
+      automatic logic [1:0]  csignals_1;
+      automatic logic [2:0]  csignals_2;
+      automatic logic        _GEN_5;
+      automatic logic        _GEN_6;
+      _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
+      _id_rt_data_T = id_inst[20:16] == 5'h0;
+      _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
+      _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
+      _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
+      id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
+      _csignals_T_3 = id_inst[31:26] == 6'h2B;
+      _csignals_T_9 = _GEN_1 == 12'h22;
+      _csignals_T_11 = _GEN_1 == 12'h24;
+      _csignals_T_13 = _GEN_1 == 12'h25;
+      _csignals_T_15 = _GEN_1 == 12'h26;
+      _csignals_T_17 = id_inst[31:26] == 6'hC;
+      _csignals_T_19 = id_inst[31:26] == 6'hD;
+      _csignals_T_21 = _GEN_1 == 12'h2A;
+      _csignals_T_23 = id_inst[31:26] == 6'h4;
+      _csignals_T_25 = id_inst[31:26] == 6'h5;
+      _csignals_T_27 = _GEN_2 == 17'h0;
+      _csignals_T_29 = _GEN_2 == 17'h2;
+      _csignals_T_31 = _GEN_2 == 17'h3;
+      _csignals_T_33 = id_inst[31:26] == 6'h3;
+      _csignals_T_35 = _GEN_1 == 12'h8;
+      _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
+      _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
+      csignals_1 =
+        _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
+        | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
+        | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
+          ? 2'h1
+          : 2'h2;
+      csignals_2 =
+        _csignals_T_1 | _csignals_T_3
+          ? 3'h2
+          : _csignals_T_5
+              ? 3'h1
+              : _csignals_T_7
+                  ? 3'h2
+                  : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                      ? 3'h1
+                      : _csignals_T_17 | _csignals_T_19
+                          ? 3'h2
+                          : _GEN_4
+                              ? 3'h1
+                              : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+      _GEN_5 = _csignals_T_23 | _csignals_T_25;
+      _GEN_6 =
+        _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
+      if (~stall_flg)
+        id_reg_pc <= if_reg_pc;
+      if (_id_inst_T)
+        id_reg_inst <= 32'h20000000;
+      else if (~stall_flg)
+        id_reg_inst <= io_imem_inst;
+      exe_reg_pc <= id_reg_pc;
+      if ((_csignals_T_1
+             ? 3'h2
+             : _csignals_T_3
+                 ? 3'h0
+                 : _GEN_6
+                     ? 3'h1
+                     : _GEN_5
+                         ? 3'h0
+                         : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
+          & id_inst[31:26] == 6'h0)
+        exe_reg_wb_addr <= id_inst[15:11];
+      else if (id_inst[31:26] == 6'h3)
+        exe_reg_wb_addr <= 5'h1F;
+      else
+        exe_reg_wb_addr <= id_inst[20:16];
+      if (csignals_1 == 2'h1) begin
+        if (id_inst[25:21] == 5'h0)
+          exe_reg_op1_data <= 32'h0;
+        else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
+          if (_exe_alu_out_T)
+            exe_reg_op1_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op1_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op1_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op1_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op1_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op1_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op1_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op1_data <= _GEN_0;
+          else if (~_exe_alu_out_T_28)
+            exe_reg_op1_data <= 32'h0;
+        end
+        else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
+          exe_reg_op1_data <= mem_wb_data;
+        else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
+          exe_reg_op1_data <= wb_reg_wb_data;
+        else
+          exe_reg_op1_data <= _regfile_ext_R1_data;
+      end
+      else if (csignals_1 == 2'h2)
+        exe_reg_op1_data <= id_reg_pc;
+      else
+        exe_reg_op1_data <= 32'h0;
+      if (csignals_2 == 3'h1) begin
+        if (_id_rt_data_T)
+          exe_reg_op2_data <= 32'h0;
+        else if (_id_rt_data_T_3) begin
+          if (_exe_alu_out_T)
+            exe_reg_op2_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op2_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op2_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op2_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op2_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op2_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op2_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op2_data <= _GEN_0;
+          else
+            exe_reg_op2_data <= _exe_alu_out_T_29;
+        end
+        else if (_id_rt_data_T_6)
+          exe_reg_op2_data <= mem_wb_data;
+        else if (_id_rt_data_T_9)
+          exe_reg_op2_data <= wb_reg_wb_data;
+        else
+          exe_reg_op2_data <= _regfile_ext_R0_data;
+      end
+      else if (csignals_2 == 3'h2)
+        exe_reg_op2_data <= id_imm_i_sext;
+      else if (csignals_2 == 3'h4)
+        exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
+      else
+        exe_reg_op2_data <= 32'h0;
+      exe_reg_rt_data <=
+        _id_rt_data_T
+          ? 32'h0
+          : _id_rt_data_T_3
+              ? exe_alu_out
+              : _id_rt_data_T_6
+                  ? mem_wb_data
+                  : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
+      if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_9)
+        exe_reg_exe_fun <= 5'h2;
+      else if (_csignals_T_11)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_13)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_15)
+        exe_reg_exe_fun <= 5'h5;
+      else if (_csignals_T_17)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_19)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_21)
+        exe_reg_exe_fun <= 5'h9;
+      else if (_csignals_T_23)
+        exe_reg_exe_fun <= 5'hB;
+      else if (_csignals_T_25)
+        exe_reg_exe_fun <= 5'hC;
+      else if (_csignals_T_27)
+        exe_reg_exe_fun <= 5'h6;
+      else if (_csignals_T_29)
+        exe_reg_exe_fun <= 5'h7;
+      else if (_csignals_T_31)
+        exe_reg_exe_fun <= 5'h8;
+      else if (_csignals_T_33)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_35)
+        exe_reg_exe_fun <= 5'hD;
+      else
+        exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
+      if (_csignals_T_1) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h2;
+      end
+      else if (_csignals_T_3) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else if (_GEN_6) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h1;
+      end
+      else if (_GEN_5) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else begin
+        exe_reg_rf_wen <=
+          {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
+        if (_GEN_3)
+          exe_reg_wb_sel <= 3'h1;
+        else if (_csignals_T_33)
+          exe_reg_wb_sel <= 3'h3;
+        else
+          exe_reg_wb_sel <= 3'h0;
+      end
+      exe_reg_imm_i_sext <= id_imm_i_sext;
+      mem_reg_pc <= exe_reg_pc;
+      mem_reg_wb_addr <= exe_reg_wb_addr;
+      mem_reg_rt_data <= exe_reg_rt_data;
+      mem_reg_mem_wen <= exe_reg_mem_wen;
+      mem_reg_rf_wen <= exe_reg_rf_wen;
+      mem_reg_wb_sel <= exe_reg_wb_sel;
+      mem_reg_alu_out <= exe_alu_out;
+      wb_reg_wb_addr <= mem_reg_wb_addr;
+      wb_reg_rf_wen <= mem_reg_rf_wen;
+      wb_reg_wb_data <= mem_wb_data;
+      if (exe_br_flg)
+        if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
+      else if (exe_jmp_flg)
+        if_reg_pc <= exe_alu_out;
+      else if (~stall_flg)
+        if_reg_pc <= if_reg_pc + 32'h4;
     end
-    else
-      pc_reg <= _pc_plus4_T;
   end // always @(posedge)
   regfile_32x32 regfile_ext (
-    .R0_addr (io_imem_inst[25:21]),
+    .R0_addr (id_inst[20:16]),
     .R0_en   (1'h1),
     .R0_clk  (clock),
     .R0_data (_regfile_ext_R0_data),
-    .R1_addr (io_imem_inst[20:16]),
+    .R1_addr (id_inst[25:21]),
     .R1_en   (1'h1),
     .R1_clk  (clock),
     .R1_data (_regfile_ext_R1_data),
-    .W0_addr (wb_addr),
+    .W0_addr (wb_reg_wb_addr),
-    .W0_en   (csignals_4 == 2'h1 & (|wb_addr)),
+    .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
     .W0_clk  (clock),
-    .W0_data (wb_data)
+    .W0_data (wb_reg_wb_data)
   );
-  assign io_imem_addr = pc_reg;
+  assign io_imem_addr = if_reg_pc;
-  assign io_dmem_addr = alu_out;
+  assign io_dmem_addr = mem_reg_alu_out;
-  assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3;
+  assign io_dmem_wen = mem_reg_mem_wen[0];
-  assign io_dmem_wdata = rt_data;
+  assign io_dmem_wdata = mem_reg_rt_data;
-  assign io_exit = io_imem_inst == 32'h114514;
+  assign io_exit = id_reg_inst == 32'h114514;
 endmodule
 
 // VCS coverage exclude_file
-module mem_4096x8(
+module mem_64x32(
-  input  [11:0] R0_addr,
+  input  [5:0]  R0_addr,
   input         R0_en,
                 R0_clk,
-  output [7:0]  R0_data,
+  output [31:0] R0_data,
-  input  [11:0] R1_addr,
+  input  [5:0]  R1_addr,
   input         R1_en,
                 R1_clk,
-  output [7:0]  R1_data,
+  output [31:0] R1_data,
-  input  [11:0] R2_addr,
+  input  [5:0]  W0_addr,
-  input         R2_en,
-                R2_clk,
-  output [7:0]  R2_data,
-  input  [11:0] R3_addr,
-  input         R3_en,
-                R3_clk,
-  output [7:0]  R3_data,
-  input  [11:0] R4_addr,
-  input         R4_en,
-                R4_clk,
-  output [7:0]  R4_data,
-  input  [11:0] R5_addr,
-  input         R5_en,
-                R5_clk,
-  output [7:0]  R5_data,
-  input  [11:0] R6_addr,
-  input         R6_en,
-                R6_clk,
-  output [7:0]  R6_data,
-  input  [11:0] R7_addr,
-  input         R7_en,
-                R7_clk,
-  output [7:0]  R7_data,
-  input  [11:0] W0_addr,
   input         W0_en,
                 W0_clk,
-  input  [7:0]  W0_data,
+  input  [31:0] W0_data
-  input  [11:0] W1_addr,
-  input         W1_en,
-                W1_clk,
-  input  [7:0]  W1_data,
-  input  [11:0] W2_addr,
-  input         W2_en,
-                W2_clk,
-  input  [7:0]  W2_data,
-  input  [11:0] W3_addr,
-  input         W3_en,
-                W3_clk,
-  input  [7:0]  W3_data
 );
 
-  reg [7:0] Memory[0:4095];
+  reg [31:0] Memory[0:63];
   always @(posedge W0_clk) begin
     if (W0_en & 1'h1)
       Memory[W0_addr] <= W0_data;
-    if (W1_en & 1'h1)
-      Memory[W1_addr] <= W1_data;
-    if (W2_en & 1'h1)
-      Memory[W2_addr] <= W2_data;
-    if (W3_en & 1'h1)
-      Memory[W3_addr] <= W3_data;
   end // always @(posedge)
   `ifdef ENABLE_INITIAL_MEM_
     initial
-      $readmemh("src/hex/mem.hex", Memory);
+      $readmemh("src/hex/mem.dat", Memory);
   `endif // ENABLE_INITIAL_MEM_
-  assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
+  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
-  assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
+  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
-  assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
-  assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
-  assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
-  assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
-  assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
-  assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
 endmodule
 
 module Memory(
@@ -369,71 +466,20 @@ module Memory(
   input  [31:0] io_dmem_wdata
 );
 
-  wire [7:0]  _mem_ext_R0_data;
+  mem_64x32 mem_ext (
-  wire [7:0]  _mem_ext_R1_data;
+    .R0_addr (io_imem_addr[7:2]),
-  wire [7:0]  _mem_ext_R2_data;
-  wire [7:0]  _mem_ext_R3_data;
-  wire [7:0]  _mem_ext_R4_data;
-  wire [7:0]  _mem_ext_R5_data;
-  wire [7:0]  _mem_ext_R6_data;
-  wire [7:0]  _mem_ext_R7_data;
-  wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
-  wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
-  wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
-  mem_4096x8 mem_ext (
-    .R0_addr (io_imem_addr[11:0]),
     .R0_en   (1'h1),
     .R0_clk  (clock),
-    .R0_data (_mem_ext_R0_data),
+    .R0_data (io_imem_inst),
-    .R1_addr (io_imem_addr[11:0] + 12'h1),
+    .R1_addr (io_dmem_addr[7:2]),
     .R1_en   (1'h1),
     .R1_clk  (clock),
-    .R1_data (_mem_ext_R1_data),
+    .R1_data (io_dmem_rdata),
-    .R2_addr (io_imem_addr[11:0] + 12'h2),
+    .W0_addr (io_dmem_addr[7:2]),
-    .R2_en   (1'h1),
-    .R2_clk  (clock),
-    .R2_data (_mem_ext_R2_data),
-    .R3_addr (io_imem_addr[11:0] + 12'h3),
-    .R3_en   (1'h1),
-    .R3_clk  (clock),
-    .R3_data (_mem_ext_R3_data),
-    .R4_addr (io_dmem_addr[11:0]),
-    .R4_en   (1'h1),
-    .R4_clk  (clock),
-    .R4_data (_mem_ext_R4_data),
-    .R5_addr (_io_dmem_rdata_T_6),
-    .R5_en   (1'h1),
-    .R5_clk  (clock),
-    .R5_data (_mem_ext_R5_data),
-    .R6_addr (_io_dmem_rdata_T_3),
-    .R6_en   (1'h1),
-    .R6_clk  (clock),
-    .R6_data (_mem_ext_R6_data),
-    .R7_addr (_io_dmem_rdata_T),
-    .R7_en   (1'h1),
-    .R7_clk  (clock),
-    .R7_data (_mem_ext_R7_data),
-    .W0_addr (_io_dmem_rdata_T),
     .W0_en   (io_dmem_wen),
     .W0_clk  (clock),
-    .W0_data (io_dmem_wdata[31:24]),
+    .W0_data (io_dmem_wdata)
-    .W1_addr (_io_dmem_rdata_T_3),
-    .W1_en   (io_dmem_wen),
-    .W1_clk  (clock),
-    .W1_data (io_dmem_wdata[23:16]),
-    .W2_addr (_io_dmem_rdata_T_6),
-    .W2_en   (io_dmem_wen),
-    .W2_clk  (clock),
-    .W2_data (io_dmem_wdata[15:8]),
-    .W3_addr (io_dmem_addr[11:0]),
-    .W3_en   (io_dmem_wen),
-    .W3_clk  (clock),
-    .W3_data (io_dmem_wdata[7:0])
   );
-  assign io_imem_inst =
-    {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
-  assign io_dmem_rdata =
-    {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
 endmodule
 
 module TopOrigin(

project/project/target/config-classes/$6080031bccf8a03d91ba.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/project/target/config-classes/$9fddc3a6676a1ed50a85.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/target/config-classes/$87709882d327edfdfbe4.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/target/config-classes/$92eace74df3dd60b2407.cache

@@ -1 +0,0 @@
-root

project/target/config-classes/$b99baa0e80f987ddc888.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/target/config-classes/$bc99ac17cdce7fb9c74c.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/target/scala-2.12/sbt-1.0/sync/copy-resource

@@ -1 +0,0 @@
-[[{},{}],{}]

project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs

@@ -1 +0,0 @@
--1800574483

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp

@@ -1 +0,0 @@
-644413116

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +0,0 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

project/target/streams/_global/update/_global/streams/out

@@ -1,3 +0,0 @@
-[debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/"), "micore-build")...
-[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/"), "micore-build")

project/target/streams/compile/_global/_global/compileOutputs/previous

@@ -1 +0,0 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

project/target/streams/compile/_global/_global/discoveredMainClasses/data

@@ -1 +0,0 @@
-[]

project/target/streams/compile/compileIncremental/_global/streams/out

@@ -1,6 +0,0 @@
-[debug] [zinc] IncrementalCompile -----------
-[debug] IncrementalCompile.incrementalCompile
-[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries
-[debug] current source = Set()
-[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
-[debug] Full compilation, no sources in previous analysis.

project/target/streams/compile/copyResources/_global/streams/out

@@ -1,2 +0,0 @@
-[debug] Copy resource mappings: 
-[debug] 	

project/target/streams/compile/exportedProducts/_global/streams/export

@@ -1 +0,0 @@
-/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes

project/target/streams/compile/incOptions/_global/streams/out

@@ -1,5 +0,0 @@
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] About to delete class files:
-[debug] We backup class files:
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak

project/target/streams/compile/internalDependencyClasspath/_global/streams/export

@@ -1 +0,0 @@
-

project/target/streams/compile/unmanagedClasspath/_global/streams/export

@@ -1 +0,0 @@
-

project/target/streams/compile/unmanagedJars/_global/streams/export

@@ -1 +0,0 @@
-

project/target/streams/runtime/exportedProducts/_global/streams/export

@@ -1 +0,0 @@
-/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/internalDependencyClasspath/_global/streams/export

@@ -1 +0,0 @@
-/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/unmanagedClasspath/_global/streams/export

@@ -1 +0,0 @@
-

project/target/streams/runtime/unmanagedJars/_global/streams/export

@@ -1 +0,0 @@
-

src/hex/addi.hex

@@ -2,6 +2,10 @@
 00
 09
 20
+01
+00
+08
+21
 14
 45
 11

src/hex/mem.dat

@@ -0,0 +1,9 @@
+20080001
+20100000
+20120065
+02088020
+21080001
+0112502a
+1540fffc
+00000000
+00114514

src/hex/mem.hex

@@ -6,7 +6,7 @@
 00
 10
 20
-05
+65
 00
 12
 20

src/main/scala/common/Consts.scala

@@ -7,7 +7,7 @@ object Consts {
   // 数据宽度和地址
   val WORD_LEN = 32 // 指令和数据的宽度为32位
   val START_ADDR = 0x00000000.U(WORD_LEN.W) // MIPS程序的起始地址通常为0x00400000
-  val BUBBLE = 0x20090000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP]
+  val BUBBLE = 0x20000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP]
   val UNIMP = 0x00114514.U(WORD_LEN.W) // 未实现指令
 
   // 寄存器地址长度

src/main/scala/micore/Core.scala

@@ -15,16 +15,15 @@ class Core extends Module {
   val regfile = Mem(32, UInt(WORD_LEN.W))
 
   // ********* Pipeline Registers *********
-  // IF/ID stage
+  // IF/ID state
   val id_reg_pc = RegInit(0.U(WORD_LEN.W))
   val id_reg_inst = RegInit(0.U(WORD_LEN.W))
 
-  // ID/EX stage
+  // ID/EX state
   val exe_reg_pc = RegInit(0.U(WORD_LEN.W))
   val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
   val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W))
   val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_rs_data = RegInit(0.U(WORD_LEN.W))
   val exe_reg_rt_data = RegInit(0.U(WORD_LEN.W))
   val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W))
   val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
@@ -33,16 +32,16 @@ class Core extends Module {
   val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W))
   val exe_reg_imm_j = RegInit(0.U(WORD_LEN.W))
 
-  // EX/MEM stage
+  // EX/MEM state
   val mem_reg_pc = RegInit(0.U(WORD_LEN.W))
   val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-  val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
   val mem_reg_rt_data = RegInit(0.U(WORD_LEN.W))
   val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
   val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W))
   val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
+  val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
 
-  // MEM/WB stage
+  // MEM/WB state
   val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
   val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W))
   val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W))
@@ -64,7 +63,7 @@ class Core extends Module {
     Seq(
       exe_br_flg -> exe_br_target,
       exe_jmp_flg -> exe_alu_out,
-      stall_flg -> if_reg_pc // stall
+      stall_flg -> if_reg_pc
     )
   )
   if_reg_pc := if_pc_next
@@ -80,37 +79,39 @@ class Core extends Module {
   )
 
   // ********* Decode (ID) Stage *********
-  val id_rs_addr = id_reg_inst(25, 21)
+  val id_rs_addr_b = id_reg_inst(25, 21)
-  val id_rt_addr = id_reg_inst(20, 16)
+  val id_rt_addr_b = id_reg_inst(20, 16)
-  val id_rd_addr = id_reg_inst(15, 11)
 
-  // Hazard detection
+  // Data hazard detection
   val id_rs_data_hazard =
-    (exe_reg_rf_wen === REN_S) && (id_rs_addr =/= 0.U) && (id_rs_addr === exe_reg_wb_addr)
+    (exe_reg_rf_wen === REN_S) && (id_rs_addr_b =/= 0.U) && (id_rs_addr_b === exe_reg_wb_addr)
   val id_rt_data_hazard =
-    (exe_reg_rf_wen === REN_S) && (id_rt_addr =/= 0.U) && (id_rt_addr === exe_reg_wb_addr)
+    (exe_reg_rf_wen === REN_S) && (id_rt_addr_b =/= 0.U) && (id_rt_addr_b === exe_reg_wb_addr)
-  stall_flg := (id_rs_data_hazard || id_rt_data_hazard) && !(exe_reg_wb_sel === WB_MEM)
+  stall_flg := (id_rs_data_hazard || id_rt_data_hazard)
-  // stall_flg := 0.U(1.W)
 
   val id_inst =
     Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
 
-  val id_rs_data = MuxCase(
+  val id_rs_addr = id_inst(25, 21)
-    regfile(id_rs_addr),
+  val id_rt_addr = id_inst(20, 16)
+  val id_rd_addr = id_inst(15, 11)
+
+  val mem_wb_data = Wire(UInt(WORD_LEN.W))
+
+  def getForwardedData(addr: UInt): UInt = {
+  MuxCase(
+    regfile(addr),
     Seq(
-      (id_rs_addr === 0.U) -> 0.U(WORD_LEN.W),
+      (addr === 0.U) -> 0.U(WORD_LEN.W),
-      ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_reg_alu_out, // Forwarding from MEM
+      ((addr === exe_reg_wb_addr) && (exe_reg_rf_wen === REN_S)) -> exe_alu_out,
-      ((id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forwarding from WB
+      ((addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data,
-    )
+      ((addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data
-  )
-  val id_rt_data = MuxCase(
-    regfile(id_rt_addr),
-    Seq(
-      (id_rt_addr === 0.U) -> 0.U(WORD_LEN.W),
-      ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_reg_alu_out, // Forwarding from MEM
-      ((id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forwarding from WB
     )
   )
+}
+
+  val id_rs_data = getForwardedData(id_rs_addr)
+  val id_rt_data = getForwardedData(id_rt_addr)
 
   val id_imm_i = id_inst(15, 0)
   val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i)
@@ -144,20 +145,13 @@ class Core extends Module {
   val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil =
     csignals
 
-  val id_op1_data = MuxCase(
+  val id_op1_data = Mux(id_op1_sel === OP1_RS1, id_rs_data, Mux(id_op1_sel === OP1_PC, id_reg_pc, 0.U(WORD_LEN.W)))
-    0.U(WORD_LEN.W),
-    Seq(
-      (id_op1_sel === OP1_RS1) -> id_rs_data,
-      (id_op1_sel === OP1_PC) -> id_reg_pc
-    )
-  )
 
-  val id_op2_data = MuxCase(
+  val id_op2_data = Mux(
-    0.U(WORD_LEN.W),
+    id_op2_sel === OP2_RS2, id_rt_data,
-    Seq(
+    Mux(
-      (id_op2_sel === OP2_RS2) -> id_rt_data,
+      id_op2_sel === OP2_IMI, id_imm_i_sext,
-      (id_op2_sel === OP2_IMI) -> id_imm_i_sext,
+      Mux(id_op2_sel === OP2_IMJ, id_imm_j, 0.U(WORD_LEN.W))
-      (id_op2_sel === OP2_IMJ) -> id_imm_j
     )
   )
 
@@ -165,15 +159,11 @@ class Core extends Module {
   exe_reg_pc := id_reg_pc
   exe_reg_op1_data := id_op1_data
   exe_reg_op2_data := id_op2_data
-  exe_reg_rs_data := id_rs_data
   exe_reg_rt_data := id_rt_data
   exe_reg_wb_addr := MuxCase(
     id_rt_addr,
     Seq(
-      (id_wb_sel === WB_ALU && id_inst(
+      (id_wb_sel === WB_ALU && id_inst(31, 26) === "b000000".U) -> id_rd_addr,
-        31,
-        26
-      ) === "b000000".U) -> id_rd_addr, // R-type
       (id_inst === JAL) -> 31.U
     )
   )
@@ -193,18 +183,9 @@ class Core extends Module {
       (exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data),
       (exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data),
       (exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data),
-      (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data(
+      (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data(4, 0))(31, 0),
-        4,
+      (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data(4, 0)).asUInt,
-        0
+      (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(4, 0)).asUInt,
-      ))(31, 0),
-      (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data(
-        4,
-        0
-      )).asUInt,
-      (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(
-        4,
-        0
-      )).asUInt,
       (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt,
       (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data
     )
@@ -214,7 +195,7 @@ class Core extends Module {
     false.B,
     Seq(
       (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data),
-      (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data)
+      (exe_reg_exe_fun === BR_BNE) -> (exe_reg_op1_data =/= exe_reg_op2_data)
     )
   )
 
@@ -223,30 +204,27 @@ class Core extends Module {
 
   // ********* Execute/Memory (EX/MEM) Stage *********
   mem_reg_pc := exe_reg_pc
+  mem_reg_rt_data := exe_reg_rt_data
   mem_reg_wb_addr := exe_reg_wb_addr
   mem_reg_alu_out := exe_alu_out
-  mem_reg_rt_data := exe_reg_rt_data
-  mem_reg_mem_wen := exe_reg_mem_wen
   mem_reg_rf_wen := exe_reg_rf_wen
   mem_reg_wb_sel := exe_reg_wb_sel
+  mem_reg_mem_wen := exe_reg_mem_wen
 
   // ********* Memory (MEM) Stage *********
   io.dmem.addr := mem_reg_alu_out
   io.dmem.wen := mem_reg_mem_wen
   io.dmem.wdata := mem_reg_rt_data
 
-  val mem_wb_data = MuxCase(
+  mem_wb_data := Mux(
-    mem_reg_alu_out,
+  mem_reg_wb_sel === WB_MEM, io.dmem.rdata,
-    Seq(
+  Mux(mem_reg_wb_sel === WB_PC, mem_reg_pc + 4.U(WORD_LEN.W), mem_reg_alu_out)
-      (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata,
+) 
-      (mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W))
-    )
-  )
 
   // ********* Memory/Write Back (MEM/WB) Stage *********
-  wb_reg_wb_addr := mem_reg_wb_addr
-  wb_reg_rf_wen := mem_reg_rf_wen
   wb_reg_wb_data := mem_wb_data
+  wb_reg_rf_wen := mem_reg_rf_wen
+  wb_reg_wb_addr := mem_reg_wb_addr
 
   // ********* Write Back (WB) Stage *********
   when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) {
@@ -254,292 +232,35 @@ class Core extends Module {
   }
 
   io.exit := (id_reg_inst === UNIMP)
-
+  // printf(p"---------------\n")
-  // ********* Debugging *********
+  // printf(p"if_inst: 0x${Hexadecimal(if_inst)}\n")
-  printf(p"---------------\n")
+  // printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n")
-  printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n")
+  // printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n")
-  printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n")
+  // printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n")
-  printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n")
+  // printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n")
-  printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n")
+  // printf(p"id_rs_data: 0x${Hexadecimal(id_rs_data)}\n")
-  printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n")
+  // printf(p"id_rt_data: 0x${Hexadecimal(id_rt_data)}\n")
-  printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n")
+  // printf(p"id_rs_addr: 0x${Hexadecimal(id_rs_addr)}\n")
-  printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n")
+  // printf(p"id_rt_addr: 0x${Hexadecimal(id_rt_addr)}\n")
-  printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n")
+  // printf(p"id_rd_addr: 0x${Hexadecimal(id_rd_addr)}\n")
-  printf(p"---------------\n")
+  // printf(p"id_imm_i_sext: 0x${Hexadecimal(id_imm_i_sext)}\n")
-}
+  // printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n")
-// package micore
+  // printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n")
-
+  // printf(p"id_rs_data_hazard: 0x${Hexadecimal(id_rs_data_hazard)}\n")
-// import chisel3._
+  // printf(p"id_rt_data_hazard: 0x${Hexadecimal(id_rt_data_hazard)}\n")
-// import chisel3.util._
+  // printf(p"stall_flg: 0x${Hexadecimal(stall_flg)}\n")
-// import common.Consts._
+  // printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n")
-// import common.Instructions._
+  // printf(p"exe_reg_op1_data: 0x${Hexadecimal(exe_reg_op1_data)}\n")
-
+  // printf(p"exe_reg_op2_data: 0x${Hexadecimal(exe_reg_op2_data)}\n")
-// class Core extends Module {
+  // printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n")
-//   val io = IO(new Bundle {
+  // printf(p"exe_br_target: 0x${Hexadecimal(exe_br_target)}\n")
-//     val imem = Flipped(new ImemPortIo())
+  // printf(p"exe_reg_wb_addr: 0x${Hexadecimal(exe_reg_wb_addr)}\n")
-//     val dmem = Flipped(new DmemPortIo())
+  // printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n")
-//     val exit = Output(Bool())
+  // printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n")
-//   })
+  // printf(p"wb_reg_wb_addr: 0x${Hexadecimal(wb_reg_wb_addr)}\n")
-
+  // printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n")
-//   val regfile = Mem(32, UInt(WORD_LEN.W))
+  // printf(p"regfile s0: ${(regfile(16.U))}\n")
-
+  // printf(p"regfile s2: ${(regfile(18.U))}\n")
-//   // ********* Pipeline Registers *********
+  // printf(p"regfile t0: ${(regfile(8.U))}\n")
-//   // IF/ID state
+  // printf(p"---------------\n")
-//   val id_reg_pc = RegInit(0.U(WORD_LEN.W))
+}
-//   val id_reg_inst = RegInit(0.U(WORD_LEN.W))
-
-//   // ID/EX state
-//   val exe_reg_pc = RegInit(0.U(WORD_LEN.W))
-//   val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-//   val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W))
-//   val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W))
-//   val exe_reg_rt_data = RegInit(0.U(WORD_LEN.W))
-//   val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W))
-//   val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
-//   val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W))
-//   val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
-//   val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W))
-//   val exe_reg_imm_j = RegInit(0.U(WORD_LEN.W))
-
-//   // EX/MEM state
-//   val mem_reg_pc = RegInit(0.U(WORD_LEN.W))
-//   val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-//   val mem_reg_rt_data = RegInit(0.U(WORD_LEN.W))
-//   val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
-//   val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W))
-//   val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
-//   val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
-
-//   // MEM/WB state
-//   val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-//   val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W))
-//   val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W))
-
-//   // ********* Instruction Fetch (IF) Stage *********
-//   val if_reg_pc = RegInit(START_ADDR)
-//   io.imem.addr := if_reg_pc
-//   val if_inst = io.imem.inst
-
-//   val stall_flg = Wire(Bool())
-//   val exe_br_flg = Wire(Bool())
-//   val exe_br_target = Wire(UInt(WORD_LEN.W))
-//   val exe_jmp_flg = Wire(Bool())
-//   val exe_alu_out = Wire(UInt(WORD_LEN.W))
-
-//   val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W)
-//   val if_pc_next = MuxCase(
-//     if_pc_plus4,
-//     Seq(
-//       exe_br_flg -> exe_br_target,
-//       exe_jmp_flg -> exe_alu_out,
-//       stall_flg -> if_reg_pc // stall
-//     )
-//   )
-//   if_reg_pc := if_pc_next
-
-//   // ********* IF/ID Stage *********
-//   id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc)
-//   id_reg_inst := MuxCase(
-//     if_inst,
-//     Seq(
-//       (exe_br_flg || exe_jmp_flg) -> BUBBLE,
-//       stall_flg -> id_reg_inst
-//     )
-//   )
-
-//   // ********* Decode (ID) Stage *********
-//   val id_rs_addr = id_reg_inst(25, 21)
-//   val id_rt_addr = id_reg_inst(20, 16)
-//   val id_rd_addr = id_reg_inst(15, 11)
-
-//   // Data hazard detection
-//   val id_rs_data_hazard =
-//     (exe_reg_rf_wen === REN_S) && (id_rs_addr =/= 0.U) && (id_rs_addr === exe_reg_wb_addr)
-//   val id_rt_data_hazard =
-//     (exe_reg_rf_wen === REN_S) && (id_rt_addr =/= 0.U) && (id_rt_addr === exe_reg_wb_addr)
-//   stall_flg := 0.U(1.W)
-//   // stall_flg := (id_rs_data_hazard || id_rt_data_hazard)
-
-//   val id_inst =
-//     Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
-
-//   val mem_wb_data = Wire(UInt(WORD_LEN.W))
-//   val id_rs_data = MuxCase(
-//     regfile(id_rs_addr),
-//     Seq(
-//       (id_rs_addr === 0.U) -> 0.U(WORD_LEN.W),
-//       ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM
-//       ((id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forward from WB
-//     )
-//   )
-//   val id_rt_data = MuxCase(
-//     regfile(id_rt_addr),
-//     Seq(
-//       (id_rt_addr === 0.U) -> 0.U(WORD_LEN.W),
-//       ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM
-//       ((id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forward from WB
-//     )
-//   )
-
-//   val id_imm_i = id_inst(15, 0)
-//   val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i)
-//   val id_imm_j = Cat(id_inst(25, 0), Fill(2, 0.U(1.W)))
-
-//   val csignals = ListLookup(
-//     id_inst,
-//     List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-//     Array(
-//       LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM),
-//       SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_X, WB_X),
-//       ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-//       SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-//       ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-//       SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-//       BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-//       SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-//       JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
-//       JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X)
-//     )
-//   )
-
-//   val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil =
-//     csignals
-
-//   val id_op1_data = MuxCase(
-//     0.U(WORD_LEN.W),
-//     Seq(
-//       (id_op1_sel === OP1_RS1) -> id_rs_data,
-//       (id_op1_sel === OP1_PC) -> id_reg_pc
-//     )
-//   )
-
-//   val id_op2_data = MuxCase(
-//     0.U(WORD_LEN.W),
-//     Seq(
-//       (id_op2_sel === OP2_RS2) -> id_rt_data,
-//       (id_op2_sel === OP2_IMI) -> id_imm_i_sext,
-//       (id_op2_sel === OP2_IMJ) -> id_imm_j
-//     )
-//   )
-
-//   // ********* Decode/Execute (ID/EX) Stage *********
-//   exe_reg_pc := id_reg_pc
-//   exe_reg_op1_data := id_op1_data
-//   exe_reg_op2_data := id_op2_data
-//   exe_reg_rt_data := id_rt_data
-//   exe_reg_wb_addr := MuxCase(
-//     id_rt_addr,
-//     Seq(
-//       (id_wb_sel === WB_ALU && id_inst(
-//         31,
-//         26
-//       ) === "b000000".U) -> id_rd_addr, // R-type
-//       (id_inst === JAL) -> 31.U
-//     )
-//   )
-//   exe_reg_wb_sel := id_wb_sel
-//   exe_reg_mem_wen := id_mem_wen
-//   exe_reg_rf_wen := id_rf_wen
-//   exe_reg_imm_i_sext := id_imm_i_sext
-//   exe_reg_imm_j := id_imm_j
-//   exe_reg_exe_fun := id_exe_fun
-
-//   // ********* Execute (EX) Stage *********
-//   exe_alu_out := MuxCase(
-//     0.U(WORD_LEN.W),
-//     Seq(
-//       (exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data),
-//       (exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data),
-//       (exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data),
-//       (exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data),
-//       (exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data),
-//       (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data(
-//         4,
-//         0
-//       ))(31, 0),
-//       (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data(
-//         4,
-//         0
-//       )).asUInt,
-//       (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(
-//         4,
-//         0
-//       )).asUInt,
-//       (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt,
-//       (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data
-//     )
-//   )
-
-//   exe_br_flg := MuxCase(
-//     false.B,
-//     Seq(
-//       (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data),
-//       (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data)
-//     )
-//   )
-
-//   exe_br_target := exe_reg_pc + (exe_reg_imm_i_sext << 2.U(5.W))
-//   exe_jmp_flg := (exe_reg_wb_sel === WB_PC)
-
-//   // ********* Execute/Memory (EX/MEM) Stage *********
-//   mem_reg_pc := exe_reg_pc
-//   mem_reg_rt_data := exe_reg_rt_data
-//   mem_reg_wb_addr := exe_reg_wb_addr
-//   mem_reg_alu_out := exe_alu_out
-//   mem_reg_rf_wen := exe_reg_rf_wen
-//   mem_reg_wb_sel := exe_reg_wb_sel
-//   mem_reg_mem_wen := exe_reg_mem_wen
-
-//   // ********* Memory (MEM) Stage *********
-//   io.dmem.addr := mem_reg_alu_out
-//   io.dmem.wen := mem_reg_mem_wen
-//   io.dmem.wdata := mem_reg_rt_data
-
-//   mem_wb_data := MuxCase(
-//     mem_reg_alu_out,
-//     Seq(
-//       (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata,
-//       (mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W))
-//     )
-//   )
-
-//   // ********* Memory/Write Back (MEM/WB) Stage *********
-//   wb_reg_wb_data := mem_wb_data
-//   wb_reg_rf_wen := mem_reg_rf_wen
-//   wb_reg_wb_addr := mem_reg_wb_addr
-
-//   // ********* Write Back (WB) Stage *********
-//   when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) {
-//     regfile(wb_reg_wb_addr) := wb_reg_wb_data
-//   }
-
-//   io.exit := (id_reg_inst === UNIMP)
-
-//   // ********* Debugging *********
-//   printf(p"---------------\n")
-//   printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n")
-//   printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n")
-//   printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n")
-//   printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n")
-//   printf(p"id_rs_data: 0x${Hexadecimal(id_rs_data)}\n")
-//   printf(p"id_rt_data: 0x${Hexadecimal(id_rt_data)}\n")
-//   printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n")
-//   printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n")
-//   printf(p"stall_flg: 0x${Hexadecimal(stall_flg)}\n")
-//   printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n")
-//   printf(p"exe_reg_op1_data: 0x${Hexadecimal(exe_reg_op1_data)}\n")
-//   printf(p"exe_reg_op2_data: 0x${Hexadecimal(exe_reg_op2_data)}\n")
-//   printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n")
-//   printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n")
-//   printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n")
-//   printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n")
-//   printf(p"---------------\n")
-// }

src/main/scala/micore/Memory.scala

@@ -16,35 +16,50 @@ class DmemPortIo extends Bundle {
   val wen = Input(Bool())
   val wdata = Input(UInt(WORD_LEN.W))
 }
-
+// TODO: 把Imem和Dmem分开方便改Cache
 class Memory extends Module {
   val io = IO(new Bundle {
     val imem = new ImemPortIo()
     val dmem = new DmemPortIo()
   })
 
-  val mem = Mem(4096, UInt(8.W))
+  val mem = Mem(64,UInt(WORD_LEN.W))
-
+  loadMemoryFromFileInline(mem, "src/hex/mem.dat")
-  loadMemoryFromFileInline(mem, "src/hex/mem.hex")
+  io.imem.inst := mem((io.imem.addr >> 2.U)(5, 0))
-
+  io.dmem.rdata := mem((io.dmem.addr >> 2.U)(5, 0))
-  io.imem.inst := Cat(
+  when(io.dmem.wen){
-    mem(io.imem.addr + 3.U(WORD_LEN.W)),
+    mem((io.dmem.addr >> 2.U)(5, 0)) := io.dmem.wdata
-    mem(io.imem.addr + 2.U(WORD_LEN.W)),
-    mem(io.imem.addr + 1.U(WORD_LEN.W)),
-    mem(io.imem.addr)
-  )
-
-  io.dmem.rdata := Cat(
-    mem(io.dmem.addr + 3.U(WORD_LEN.W)),
-    mem(io.dmem.addr + 2.U(WORD_LEN.W)),
-    mem(io.dmem.addr + 1.U(WORD_LEN.W)),
-    mem(io.dmem.addr)
-  )
-
-  when(io.dmem.wen) {
-    mem(io.dmem.addr) := io.dmem.wdata(7, 0)
-    mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)
-    mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)
-    mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(31, 24)
   }
+  // * 32'h20080001,  // li $t0, 1 (addi $t0, $zero, 1)
+  // * 32'h20100000,  // li $s0, 0 (addi $s0, $zero, 0)
+  // * 32'h20120006,  // li $s2, 6 (addi $s2, $zero, 6)
+
+  // * 32'h02088020,  // add $s0, $s0, $t0
+  // * 32'h21080001,  // addi $t0, $t0, 1
+  // * 32'h0112502A,  // slt $t2, $t0, $s2
+  // * 32'h1540FFFC,  // bne $t2, $zero, loop (branch back to loop if $t2 != 0)
+  // val mem = Mem(256, UInt(8.W))
+
+  // loadMemoryFromFileInline(mem, "src/hex/mem.hex")
+
+  // io.imem.inst := Cat(
+  //   mem(io.imem.addr + 3.U(WORD_LEN.W)),
+  //   mem(io.imem.addr + 2.U(WORD_LEN.W)),
+  //   mem(io.imem.addr + 1.U(WORD_LEN.W)),
+  //   mem(io.imem.addr)
+  // )
+
+  // io.dmem.rdata := Cat(
+  //   mem(io.dmem.addr + 3.U(WORD_LEN.W)),
+  //   mem(io.dmem.addr + 2.U(WORD_LEN.W)),
+  //   mem(io.dmem.addr + 1.U(WORD_LEN.W)),
+  //   mem(io.dmem.addr)
+  // )
+
+  // when(io.dmem.wen) {
+  //   mem(io.dmem.addr) := io.dmem.wdata(7, 0)
+  //   mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)
+  //   mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)
+  //   mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(31, 24)
+  // }
 }

src/test/scala/micore/MicoreSpec.scala

@@ -5,11 +5,11 @@ import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
-class CTest extends AnyFlatSpec with ChiselScalatestTester {
+class PipelineTest extends AnyFlatSpec with ChiselScalatestTester {
-  "Micore" should "run the C program" in {
+  "Micore" should "run the test program" in {
     test(new TopOrigin) { c =>
       while (!c.io.exit.peek().litToBoolean) { c.clock.step(1) }
-      c.clock.step(1)
+      // for (i <- 0 until 24) { c.clock.step(1) }
     }
   }
 }

target/scala-2.13/sync/copy-resource

@@ -1 +0,0 @@
-[[{},{}],{}]

target/scala-2.13/update/update_cache_2.13/inputs

@@ -1 +0,0 @@
-733072008

target/streams/_global/dependencyPositions/_global/streams/update_cache_2.13/input_dsp

@@ -1 +0,0 @@
--1437776151

target/streams/_global/dependencyPositions/_global/streams/update_cache_2.13/output_dsp

@@ -1 +0,0 @@
-{"{\"organization\":\"org.chipsalliance\",\"name\":\"chisel\",\"revision\":\"6.2.0\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","startLine"],"path":"Defaults.scala","startLine":4429},"type":"LinePosition"},"{\"organization\":\"org.chipsalliance\",\"name\":\"chisel-plugin\",\"revision\":\"6.2.0\",\"configurations\":\"plugin->default(compile)\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Full\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","startLine"],"path":"Defaults.scala","startLine":4429},"type":"LinePosition"},"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.13.12\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"Defaults.scala","startLine":4429},"type":"LinePosition"},"{\"organization\":\"org.scalatest\",\"name\":\"scalatest\",\"revision\":\"3.2.16\",\"configurations\":\"test\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","startLine"],"path":"Defaults.scala","startLine":4429},"type":"LinePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chiseltest\",\"revision\":\"6.0.0\",\"configurations\":\"test\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","startLine"],"path":"Defaults.scala","startLine":4429},"type":"LinePosition"}}

target/streams/_global/update/_global/streams/out

@@ -1,3 +0,0 @@
-[debug] not up to date. inChanged = false, force = true
-[debug] Updating ...
-[debug] Done updating 

target/streams/_global/updateClassifiers/_global/streams/out

@@ -1,3 +0,0 @@
-[debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/"), "root")...
-[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/"), "root")

target/streams/_global/updateClassifiers/_global/streams/update_cache_2.13/inputs

@@ -1 +0,0 @@
--175642782

target/streams/compile/_global/_global/compileOutputs/previous

@@ -1 +0,0 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/ImemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/DmemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]

target/streams/compile/_global/_global/discoveredMainClasses/data

@@ -1 +0,0 @@
-["micore.TopOrigin","sicore.TopOrigin"]

target/streams/compile/bloopGenerate/_global/streams/out

@@ -1,4 +0,0 @@
-[debug] [root] Classpath dependencies List()
-[debug] [root] Dependencies from configurations List()
-[debug] Bloop wrote the configuration of project 'root' to '/run/media/gh0s7/Data/project/ddca2024/micore/.bloop/root.json'
-[success] Generated .bloop/root.json

target/streams/compile/bloopPostGenerate/_global/streams/out

@@ -1 +0,0 @@
-[debug] Running postGenerate for root

target/streams/compile/compile/_global/streams/out

@@ -1,4 +0,0 @@
-[error] /run/media/gh0s7/Data/project/ddca2024/micore/src/main/scala/micore/Top.scala:25:9: not found: type TopOrigin
-[error]     new TopOrigin,
-[error]         ^
-[error] one error found

target/streams/compile/copyResources/_global/streams/out

@@ -1,2 +0,0 @@
-[debug] Copy resource mappings: 
-[debug] 	

target/streams/compile/exportedProductJars/_global/streams/export

@@ -1 +0,0 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar

target/streams/compile/exportedProducts/_global/streams/export

@@ -1 +0,0 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/classes

target/streams/compile/incOptions/_global/streams/out

@@ -1,11 +0,0 @@
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak
-[debug] About to delete class files:
-[debug] 	Core$$anon$1.class
-[debug] 	Core.class
-[debug] We backup class files:
-[debug] 	Core$$anon$1.class
-[debug] 	Core.class
-[debug] Registering generated classes:
-[debug] 	Core$$anon$1.class
-[debug] 	Core.class
-[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak

target/streams/compile/internalDependencyClasspath/_global/streams/export

@@ -1 +0,0 @@
-