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7ae5ee8c39
| Author | SHA1 | Date | |
|---|---|---|---|
| 7ae5ee8c39 | |||
| 99703db0db |
612
Core.sv
612
Core.sv
@@ -1,25 +1,24 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:25:38
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// Design Name:
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// Design Name:
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// Module Name: Core
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Core(
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input clock,
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reset,
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@@ -29,10 +28,13 @@ module Core(
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input [31:0] io_dmem_rdata,
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output io_dmem_wen,
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output [31:0] io_dmem_wdata,
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output io_exit,
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output [31:0] s0_value
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output [3:0] io_anodes,
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output [6:0] io_segments,
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output io_exit
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);
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wire exe_jmp_flg;
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wire exe_br_flg;
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wire [31:0] _regfile_ext_R0_data;
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wire [31:0] _regfile_ext_R1_data;
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reg [31:0] id_reg_pc;
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@@ -41,275 +43,385 @@ module Core(
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reg [4:0] exe_reg_wb_addr;
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reg [31:0] exe_reg_op1_data;
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reg [31:0] exe_reg_op2_data;
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reg [31:0] exe_reg_rs2_data;
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reg [31:0] exe_reg_rt_data;
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reg [4:0] exe_reg_exe_fun;
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reg [1:0] exe_reg_mem_wen;
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reg [1:0] exe_reg_rf_wen;
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reg [2:0] exe_reg_wb_sel;
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reg [31:0] exe_reg_imm_b_sext;
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reg [31:0] exe_reg_imm_i_sext;
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reg [31:0] mem_reg_pc;
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reg [4:0] mem_reg_wb_addr;
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reg [31:0] mem_reg_alu_out;
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reg [31:0] mem_reg_rs2_data;
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reg [31:0] mem_reg_rt_data;
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reg [1:0] mem_reg_mem_wen;
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reg [1:0] mem_reg_rf_wen;
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reg [2:0] mem_reg_wb_sel;
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reg [1:0] mem_reg_mem_wen;
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reg [31:0] mem_reg_alu_out;
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reg [4:0] wb_reg_wb_addr;
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reg [1:0] wb_reg_rf_wen;
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reg [31:0] wb_reg_wb_data;
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reg [31:0] if_reg_pc;
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wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
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wire exe_br_flg =
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exe_reg_exe_fun == 5'hC
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? exe_reg_op1_data != exe_reg_op2_data
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: exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
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wire exe_jmp_flg = exe_reg_wb_sel == 3'h3;
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wire _id_inst_T = exe_br_flg | exe_jmp_flg;
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wire _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
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wire stall_flg =
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_id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
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| _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
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wire _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
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wire _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
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wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
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wire _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
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wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
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wire _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
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wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
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wire _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
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wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
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wire _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
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wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
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wire _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
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wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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wire _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
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wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
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wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
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wire _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
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wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
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wire _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
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wire _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
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wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
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wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
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wire [31:0] exe_alu_out =
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_exe_alu_out_T
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? _exe_alu_out_T_1
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: _exe_alu_out_T_3
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? _exe_alu_out_T_4
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: _exe_alu_out_T_6
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? _exe_alu_out_T_7
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: _exe_alu_out_T_8
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? _exe_alu_out_T_9
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: _exe_alu_out_T_10
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? _exe_alu_out_T_11
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: _exe_alu_out_T_12
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? _exe_alu_out_T_14[31:0]
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: _exe_alu_out_T_16
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? _exe_alu_out_T_18
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: _exe_alu_out_T_19
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? _exe_alu_out_T_22
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: _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
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assign exe_br_flg =
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exe_reg_exe_fun == 5'hB
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? exe_reg_op1_data == exe_reg_op2_data
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: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
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assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
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wire [31:0] mem_wb_data =
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mem_reg_wb_sel == 3'h2
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? io_dmem_rdata
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: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
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always @(posedge clock) begin
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automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg;
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automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
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automatic logic stall_flg;
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automatic logic [31:0] id_inst;
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automatic logic _id_rs2_data_T_2;
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automatic logic _id_rs2_data_T;
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automatic logic [31:0] _id_rs2_data_T_8;
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automatic logic [16:0] _GEN;
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automatic logic _csignals_T_5;
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automatic logic [19:0] _GEN_0;
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automatic logic _csignals_T_7;
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automatic logic _csignals_T_9;
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automatic logic _csignals_T_11;
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automatic logic _csignals_T_13;
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automatic logic _csignals_T_15;
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automatic logic _csignals_T_17;
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automatic logic _csignals_T_19;
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automatic logic [16:0] _GEN_1;
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automatic logic _csignals_T_21;
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automatic logic _csignals_T_23;
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automatic logic _csignals_T_25;
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automatic logic _csignals_T_27;
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automatic logic _csignals_T_29;
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automatic logic _csignals_T_31;
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automatic logic _csignals_T_33;
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automatic logic _csignals_T_35;
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automatic logic _csignals_T_37;
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automatic logic _csignals_T_39;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic [1:0] csignals_1;
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automatic logic [2:0] _csignals_T_95;
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automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
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automatic logic [62:0] _exe_alu_out_T_8 =
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{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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automatic logic [31:0] exe_alu_out;
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stall_flg =
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_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
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& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
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& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
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_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
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_id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
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_id_rs2_data_T_8 =
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id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_reg_alu_out
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: id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R0_data;
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_GEN = {id_inst[31:26], id_inst[10:0]};
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_csignals_T_5 = _GEN == 17'h20;
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_GEN_0 = {id_inst[31:28], id_inst[15:0]};
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_csignals_T_7 = _GEN_0 == 20'h80000;
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_csignals_T_9 = _GEN == 17'h22;
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_csignals_T_11 = _GEN == 17'h24;
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_csignals_T_13 = _GEN == 17'h25;
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_csignals_T_15 = _GEN == 17'h26;
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_csignals_T_17 = _GEN_0 == 20'hC0000;
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_csignals_T_19 = _GEN_0 == 20'hD0000;
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_GEN_1 = {id_inst[30:20], id_inst[5:0]};
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_csignals_T_21 = _GEN_1 == 17'h0;
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_csignals_T_23 = _GEN_1 == 17'h2;
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_csignals_T_25 = _GEN_1 == 17'h3;
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_csignals_T_27 = _GEN == 17'h2A;
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_csignals_T_29 = _GEN_0 == 20'h40000;
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_csignals_T_31 = _GEN_0 == 20'h50000;
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_csignals_T_33 = id_inst == 32'hC000000;
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_csignals_T_35 = _GEN_0 == 20'h8;
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_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
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_csignals_T_39 = id_inst == 32'h0;
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_GEN_2 = _csignals_T_29 | _csignals_T_31;
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_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
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csignals_1 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
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? 2'h0
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: _csignals_T_33
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? 2'h1
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: _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
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_csignals_T_95 =
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_csignals_T_5
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? 3'h1
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: _csignals_T_7
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? 3'h2
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: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_3
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? 3'h1
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: _csignals_T_33
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? 3'h4
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: _csignals_T_35
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? 3'h0
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: _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
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exe_alu_out =
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exe_reg_exe_fun == 5'hE
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? exe_reg_op1_data
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: exe_reg_exe_fun == 5'h9
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? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
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: exe_reg_exe_fun == 5'h8
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? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
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: exe_reg_exe_fun == 5'h7
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? exe_reg_op1_data >> _GEN_4
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: exe_reg_exe_fun == 5'h6
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? _exe_alu_out_T_8[31:0]
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: exe_reg_exe_fun == 5'h5
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? exe_reg_op1_data ^ exe_reg_op2_data
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: exe_reg_exe_fun == 5'h4
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? exe_reg_op1_data | exe_reg_op2_data
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: exe_reg_exe_fun == 5'h3
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? exe_reg_op1_data & exe_reg_op2_data
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: exe_reg_exe_fun == 5'h2
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? exe_reg_op1_data - exe_reg_op2_data
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: exe_reg_exe_fun == 5'h1
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? exe_reg_op1_data + exe_reg_op2_data
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: 32'h0;
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if (~stall_flg)
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id_reg_pc <= if_reg_pc;
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if (_id_inst_T)
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if (reset) begin
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id_reg_pc <= 32'h0;
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id_reg_inst <= 32'h0;
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else if (~stall_flg)
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id_reg_inst <= io_imem_inst;
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exe_reg_pc <= id_reg_pc;
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exe_reg_wb_addr <= id_reg_inst[15:11];
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if (csignals_1 == 2'h0)
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exe_reg_op1_data <=
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id_reg_inst[25:21] == 5'h0
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? 32'h0
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: id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_reg_alu_out
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: id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R1_data;
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else if (csignals_1 == 2'h1)
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exe_reg_op1_data <= id_reg_pc;
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else
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exe_reg_pc <= 32'h0;
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exe_reg_wb_addr <= 5'h0;
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exe_reg_op1_data <= 32'h0;
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if (_csignals_T_95 == 3'h5)
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exe_reg_op2_data <= {id_inst[15:0], 16'h0};
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else if (_csignals_T_95 == 3'h4)
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exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
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else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
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exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
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else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
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exe_reg_op2_data <= 32'h0;
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else
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exe_reg_op2_data <= _id_rs2_data_T_8;
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exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
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if (_csignals_T_5 | _csignals_T_7)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_9)
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exe_reg_exe_fun <= 5'h2;
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else if (_csignals_T_11)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_13)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_15)
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exe_reg_exe_fun <= 5'h5;
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else if (_csignals_T_17)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_19)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_21)
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exe_reg_exe_fun <= 5'h6;
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else if (_csignals_T_23)
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exe_reg_exe_fun <= 5'h7;
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else if (_csignals_T_25)
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exe_reg_exe_fun <= 5'h8;
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else if (_csignals_T_27)
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exe_reg_exe_fun <= 5'h9;
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else if (_csignals_T_29)
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exe_reg_exe_fun <= 5'hB;
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else if (_csignals_T_31)
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exe_reg_exe_fun <= 5'hC;
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else if (_csignals_T_33)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_35)
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exe_reg_exe_fun <= 5'hE;
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else
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exe_reg_exe_fun <= {4'h0, _csignals_T_37};
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exe_reg_mem_wen <= 2'h0;
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if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
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| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
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exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
end
|
||||
else if (_GEN_2) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else if (_csignals_T_33) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h3;
|
||||
end
|
||||
else if (_csignals_T_35) begin
|
||||
exe_reg_rt_data <= 32'h0;
|
||||
exe_reg_exe_fun <= 5'h0;
|
||||
exe_reg_mem_wen <= 2'h0;
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
exe_reg_imm_i_sext <= 32'h0;
|
||||
mem_reg_pc <= 32'h0;
|
||||
mem_reg_wb_addr <= 5'h0;
|
||||
mem_reg_rt_data <= 32'h0;
|
||||
mem_reg_mem_wen <= 2'h0;
|
||||
mem_reg_rf_wen <= 2'h0;
|
||||
mem_reg_wb_sel <= 3'h0;
|
||||
mem_reg_alu_out <= 32'h0;
|
||||
wb_reg_wb_addr <= 5'h0;
|
||||
wb_reg_rf_wen <= 2'h0;
|
||||
wb_reg_wb_data <= 32'h0;
|
||||
if_reg_pc <= 32'h0;
|
||||
end
|
||||
else begin
|
||||
exe_reg_rf_wen <= {1'h0, _csignals_T_37};
|
||||
exe_reg_wb_sel <= {2'h0, _csignals_T_37};
|
||||
automatic logic _id_rt_data_T_5;
|
||||
automatic logic _id_rt_data_T;
|
||||
automatic logic _id_rt_data_T_3;
|
||||
automatic logic _id_rt_data_T_6;
|
||||
automatic logic _id_rt_data_T_9;
|
||||
automatic logic [31:0] id_imm_i_sext;
|
||||
automatic logic _csignals_T_1 = id_inst[31:26] == 6'h23;
|
||||
automatic logic _csignals_T_3;
|
||||
automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
|
||||
automatic logic _csignals_T_5 = _GEN_1 == 12'h20;
|
||||
automatic logic _csignals_T_7 = id_inst[31:26] == 6'h8;
|
||||
automatic logic _csignals_T_9;
|
||||
automatic logic _csignals_T_11;
|
||||
automatic logic _csignals_T_13;
|
||||
automatic logic _csignals_T_15;
|
||||
automatic logic _csignals_T_17;
|
||||
automatic logic _csignals_T_19;
|
||||
automatic logic _csignals_T_21;
|
||||
automatic logic _csignals_T_23;
|
||||
automatic logic _csignals_T_25;
|
||||
automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
|
||||
automatic logic _csignals_T_27;
|
||||
automatic logic _csignals_T_29;
|
||||
automatic logic _csignals_T_31;
|
||||
automatic logic _csignals_T_33;
|
||||
automatic logic _csignals_T_35;
|
||||
automatic logic _GEN_3;
|
||||
automatic logic _GEN_4;
|
||||
automatic logic [1:0] csignals_1;
|
||||
automatic logic [2:0] csignals_2;
|
||||
automatic logic _GEN_5;
|
||||
automatic logic _GEN_6;
|
||||
_id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
|
||||
_id_rt_data_T = id_inst[20:16] == 5'h0;
|
||||
_id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
|
||||
_id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
|
||||
_id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
|
||||
id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
|
||||
_csignals_T_3 = id_inst[31:26] == 6'h2B;
|
||||
_csignals_T_9 = _GEN_1 == 12'h22;
|
||||
_csignals_T_11 = _GEN_1 == 12'h24;
|
||||
_csignals_T_13 = _GEN_1 == 12'h25;
|
||||
_csignals_T_15 = _GEN_1 == 12'h26;
|
||||
_csignals_T_17 = id_inst[31:26] == 6'hC;
|
||||
_csignals_T_19 = id_inst[31:26] == 6'hD;
|
||||
_csignals_T_21 = _GEN_1 == 12'h2A;
|
||||
_csignals_T_23 = id_inst[31:26] == 6'h4;
|
||||
_csignals_T_25 = id_inst[31:26] == 6'h5;
|
||||
_csignals_T_27 = _GEN_2 == 17'h0;
|
||||
_csignals_T_29 = _GEN_2 == 17'h2;
|
||||
_csignals_T_31 = _GEN_2 == 17'h3;
|
||||
_csignals_T_33 = id_inst[31:26] == 6'h3;
|
||||
_csignals_T_35 = _GEN_1 == 12'h8;
|
||||
_GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
|
||||
_GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
|
||||
csignals_1 =
|
||||
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
|
||||
| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
|
||||
| _csignals_T_19 | _GEN_4 | ~_csignals_T_33
|
||||
? 2'h1
|
||||
: 2'h2;
|
||||
csignals_2 =
|
||||
_csignals_T_1 | _csignals_T_3
|
||||
? 3'h2
|
||||
: _csignals_T_5
|
||||
? 3'h1
|
||||
: _csignals_T_7
|
||||
? 3'h2
|
||||
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
|
||||
? 3'h1
|
||||
: _csignals_T_17 | _csignals_T_19
|
||||
? 3'h2
|
||||
: _GEN_4
|
||||
? 3'h1
|
||||
: _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
|
||||
_GEN_5 = _csignals_T_23 | _csignals_T_25;
|
||||
_GEN_6 =
|
||||
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
||||
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
|
||||
if (~stall_flg)
|
||||
id_reg_pc <= if_reg_pc;
|
||||
if (_id_inst_T)
|
||||
id_reg_inst <= 32'h20000000;
|
||||
else if (~stall_flg)
|
||||
id_reg_inst <= io_imem_inst;
|
||||
exe_reg_pc <= id_reg_pc;
|
||||
if ((_csignals_T_1
|
||||
? 3'h2
|
||||
: _csignals_T_3
|
||||
? 3'h0
|
||||
: _GEN_6
|
||||
? 3'h1
|
||||
: _GEN_5
|
||||
? 3'h0
|
||||
: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
|
||||
& id_inst[31:26] == 6'h0)
|
||||
exe_reg_wb_addr <= id_inst[15:11];
|
||||
else if (id_inst[31:26] == 6'h3)
|
||||
exe_reg_wb_addr <= 5'h1F;
|
||||
else
|
||||
exe_reg_wb_addr <= id_inst[20:16];
|
||||
if (csignals_1 == 2'h1) begin
|
||||
if (id_inst[25:21] == 5'h0)
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
|
||||
if (_exe_alu_out_T)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_1;
|
||||
else if (_exe_alu_out_T_3)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_4;
|
||||
else if (_exe_alu_out_T_6)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_7;
|
||||
else if (_exe_alu_out_T_8)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_9;
|
||||
else if (_exe_alu_out_T_10)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_11;
|
||||
else if (_exe_alu_out_T_12)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
|
||||
else if (_exe_alu_out_T_16)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_18;
|
||||
else if (_exe_alu_out_T_19)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_22;
|
||||
else if (_exe_alu_out_T_24)
|
||||
exe_reg_op1_data <= _GEN_0;
|
||||
else if (~_exe_alu_out_T_28)
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
end
|
||||
else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
|
||||
exe_reg_op1_data <= mem_wb_data;
|
||||
else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
|
||||
exe_reg_op1_data <= wb_reg_wb_data;
|
||||
else
|
||||
exe_reg_op1_data <= _regfile_ext_R1_data;
|
||||
end
|
||||
else if (csignals_1 == 2'h2)
|
||||
exe_reg_op1_data <= id_reg_pc;
|
||||
else
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
if (csignals_2 == 3'h1) begin
|
||||
if (_id_rt_data_T)
|
||||
exe_reg_op2_data <= 32'h0;
|
||||
else if (_id_rt_data_T_3) begin
|
||||
if (_exe_alu_out_T)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_1;
|
||||
else if (_exe_alu_out_T_3)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_4;
|
||||
else if (_exe_alu_out_T_6)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_7;
|
||||
else if (_exe_alu_out_T_8)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_9;
|
||||
else if (_exe_alu_out_T_10)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_11;
|
||||
else if (_exe_alu_out_T_12)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
|
||||
else if (_exe_alu_out_T_16)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_18;
|
||||
else if (_exe_alu_out_T_19)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_22;
|
||||
else if (_exe_alu_out_T_24)
|
||||
exe_reg_op2_data <= _GEN_0;
|
||||
else
|
||||
exe_reg_op2_data <= _exe_alu_out_T_29;
|
||||
end
|
||||
else if (_id_rt_data_T_6)
|
||||
exe_reg_op2_data <= mem_wb_data;
|
||||
else if (_id_rt_data_T_9)
|
||||
exe_reg_op2_data <= wb_reg_wb_data;
|
||||
else
|
||||
exe_reg_op2_data <= _regfile_ext_R0_data;
|
||||
end
|
||||
else if (csignals_2 == 3'h2)
|
||||
exe_reg_op2_data <= id_imm_i_sext;
|
||||
else if (csignals_2 == 3'h4)
|
||||
exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
|
||||
else
|
||||
exe_reg_op2_data <= 32'h0;
|
||||
exe_reg_rt_data <=
|
||||
_id_rt_data_T
|
||||
? 32'h0
|
||||
: _id_rt_data_T_3
|
||||
? exe_alu_out
|
||||
: _id_rt_data_T_6
|
||||
? mem_wb_data
|
||||
: _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
|
||||
if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_9)
|
||||
exe_reg_exe_fun <= 5'h2;
|
||||
else if (_csignals_T_11)
|
||||
exe_reg_exe_fun <= 5'h3;
|
||||
else if (_csignals_T_13)
|
||||
exe_reg_exe_fun <= 5'h4;
|
||||
else if (_csignals_T_15)
|
||||
exe_reg_exe_fun <= 5'h5;
|
||||
else if (_csignals_T_17)
|
||||
exe_reg_exe_fun <= 5'h3;
|
||||
else if (_csignals_T_19)
|
||||
exe_reg_exe_fun <= 5'h4;
|
||||
else if (_csignals_T_21)
|
||||
exe_reg_exe_fun <= 5'h9;
|
||||
else if (_csignals_T_23)
|
||||
exe_reg_exe_fun <= 5'hB;
|
||||
else if (_csignals_T_25)
|
||||
exe_reg_exe_fun <= 5'hC;
|
||||
else if (_csignals_T_27)
|
||||
exe_reg_exe_fun <= 5'h6;
|
||||
else if (_csignals_T_29)
|
||||
exe_reg_exe_fun <= 5'h7;
|
||||
else if (_csignals_T_31)
|
||||
exe_reg_exe_fun <= 5'h8;
|
||||
else if (_csignals_T_33)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_35)
|
||||
exe_reg_exe_fun <= 5'hD;
|
||||
else
|
||||
exe_reg_exe_fun <= 5'h0;
|
||||
exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
|
||||
if (_csignals_T_1) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h2;
|
||||
end
|
||||
else if (_csignals_T_3) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else if (_GEN_6) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
end
|
||||
else if (_GEN_5) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else begin
|
||||
exe_reg_rf_wen <=
|
||||
{1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
|
||||
if (_GEN_3)
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
else if (_csignals_T_33)
|
||||
exe_reg_wb_sel <= 3'h3;
|
||||
else
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
exe_reg_imm_i_sext <= id_imm_i_sext;
|
||||
mem_reg_pc <= exe_reg_pc;
|
||||
mem_reg_wb_addr <= exe_reg_wb_addr;
|
||||
mem_reg_rt_data <= exe_reg_rt_data;
|
||||
mem_reg_mem_wen <= exe_reg_mem_wen;
|
||||
mem_reg_rf_wen <= exe_reg_rf_wen;
|
||||
mem_reg_wb_sel <= exe_reg_wb_sel;
|
||||
mem_reg_alu_out <= exe_alu_out;
|
||||
wb_reg_wb_addr <= mem_reg_wb_addr;
|
||||
wb_reg_rf_wen <= mem_reg_rf_wen;
|
||||
wb_reg_wb_data <= mem_wb_data;
|
||||
if (exe_br_flg)
|
||||
if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
|
||||
else if (exe_jmp_flg)
|
||||
if_reg_pc <= exe_alu_out;
|
||||
else if (~stall_flg)
|
||||
if_reg_pc <= if_reg_pc + 32'h4;
|
||||
end
|
||||
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
|
||||
mem_reg_pc <= exe_reg_pc;
|
||||
mem_reg_wb_addr <= exe_reg_wb_addr;
|
||||
mem_reg_alu_out <= exe_alu_out;
|
||||
mem_reg_rs2_data <= exe_reg_rs2_data;
|
||||
mem_reg_rf_wen <= exe_reg_rf_wen;
|
||||
mem_reg_wb_sel <= exe_reg_wb_sel;
|
||||
mem_reg_mem_wen <= exe_reg_mem_wen;
|
||||
wb_reg_wb_addr <= mem_reg_wb_addr;
|
||||
wb_reg_rf_wen <= mem_reg_rf_wen;
|
||||
wb_reg_wb_data <=
|
||||
mem_reg_wb_sel == 3'h3
|
||||
? mem_reg_pc + 32'h4
|
||||
: mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
|
||||
if (reset)
|
||||
if_reg_pc <= 32'h0;
|
||||
else if (exe_br_flg)
|
||||
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
|
||||
else if (exe_jmp_flg)
|
||||
if_reg_pc <= exe_alu_out;
|
||||
else if (~stall_flg)
|
||||
if_reg_pc <= if_reg_pc + 32'h4;
|
||||
end // always @(posedge)
|
||||
regfile_32x32 regfile_ext (
|
||||
.R0_addr (id_reg_inst[20:16]),
|
||||
.R0_addr (id_inst[20:16]),
|
||||
.R0_en (1'h1),
|
||||
.R0_clk (clock),
|
||||
.R0_data (_regfile_ext_R0_data),
|
||||
.R1_addr (id_reg_inst[25:21]),
|
||||
.R1_addr (id_inst[25:21]),
|
||||
.R1_en (1'h1),
|
||||
.R1_clk (clock),
|
||||
.R1_data (_regfile_ext_R1_data),
|
||||
.W0_addr (wb_reg_wb_addr),
|
||||
.W0_en (_id_rs2_data_T_5),
|
||||
.W0_en (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
|
||||
.W0_clk (clock),
|
||||
.io_anodes (io_anodes),
|
||||
.io_segments (io_segments),
|
||||
.W0_data (wb_reg_wb_data)
|
||||
);
|
||||
assign io_imem_addr = if_reg_pc;
|
||||
assign io_dmem_addr = mem_reg_alu_out;
|
||||
assign io_dmem_wen = mem_reg_mem_wen[0];
|
||||
assign io_dmem_wdata = mem_reg_rs2_data;
|
||||
assign io_exit = id_reg_inst == 32'h00000000;
|
||||
assign s0_value = _regfile_ext_R0_data;
|
||||
assign io_dmem_wdata = mem_reg_rt_data;
|
||||
assign io_exit = id_reg_inst == 32'h114514;
|
||||
endmodule
|
||||
|
||||
171
Memory.sv
171
Memory.sv
@@ -1,64 +1,98 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/12/28 11:28:52
|
||||
// Design Name:
|
||||
// Design Name:
|
||||
// Module Name: Regfile
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module mem_512x32(
|
||||
input [8:0] R0_addr,
|
||||
module mem_4096x8(
|
||||
input [11:0] R0_addr,
|
||||
input R0_en,
|
||||
R0_clk,
|
||||
output [31:0] R0_data,
|
||||
input [8:0] R1_addr,
|
||||
output [7:0] R0_data,
|
||||
input [11:0] R1_addr,
|
||||
input R1_en,
|
||||
R1_clk,
|
||||
output [31:0] R1_data,
|
||||
input [8:0] W0_addr,
|
||||
output [7:0] R1_data,
|
||||
input [11:0] R2_addr,
|
||||
input R2_en,
|
||||
R2_clk,
|
||||
output [7:0] R2_data,
|
||||
input [11:0] R3_addr,
|
||||
input R3_en,
|
||||
R3_clk,
|
||||
output [7:0] R3_data,
|
||||
input [11:0] R4_addr,
|
||||
input R4_en,
|
||||
R4_clk,
|
||||
output [7:0] R4_data,
|
||||
input [11:0] R5_addr,
|
||||
input R5_en,
|
||||
R5_clk,
|
||||
output [7:0] R5_data,
|
||||
input [11:0] R6_addr,
|
||||
input R6_en,
|
||||
R6_clk,
|
||||
output [7:0] R6_data,
|
||||
input [11:0] R7_addr,
|
||||
input R7_en,
|
||||
R7_clk,
|
||||
output [7:0] R7_data,
|
||||
input [11:0] W0_addr,
|
||||
input W0_en,
|
||||
W0_clk,
|
||||
input [31:0] W0_data
|
||||
input [7:0] W0_data,
|
||||
input [11:0] W1_addr,
|
||||
input W1_en,
|
||||
W1_clk,
|
||||
input [7:0] W1_data,
|
||||
input [11:0] W2_addr,
|
||||
input W2_en,
|
||||
W2_clk,
|
||||
input [7:0] W2_data,
|
||||
input [11:0] W3_addr,
|
||||
input W3_en,
|
||||
W3_clk,
|
||||
input [7:0] W3_data
|
||||
);
|
||||
|
||||
reg [31:0] Memory[0:511];
|
||||
reg _R0_en_d0;
|
||||
reg [8:0] _R0_addr_d0;
|
||||
always @(posedge R0_clk) begin
|
||||
_R0_en_d0 <= R0_en;
|
||||
_R0_addr_d0 <= R0_addr;
|
||||
end // always @(posedge)
|
||||
reg _R1_en_d0;
|
||||
reg [8:0] _R1_addr_d0;
|
||||
always @(posedge R1_clk) begin
|
||||
_R1_en_d0 <= R1_en;
|
||||
_R1_addr_d0 <= R1_addr;
|
||||
end // always @(posedge)
|
||||
reg [7:0] Memory[0:4095];
|
||||
always @(posedge W0_clk) begin
|
||||
if (W0_en & 1'h1)
|
||||
Memory[W0_addr] <= W0_data;
|
||||
if (W1_en & 1'h1)
|
||||
Memory[W1_addr] <= W1_data;
|
||||
if (W2_en & 1'h1)
|
||||
Memory[W2_addr] <= W2_data;
|
||||
if (W3_en & 1'h1)
|
||||
Memory[W3_addr] <= W3_data;
|
||||
end // always @(posedge)
|
||||
`ifdef ENABLE_INITIAL_MEM_
|
||||
initial
|
||||
$readmemh("src/hex/mem.hex", Memory);
|
||||
`endif // ENABLE_INITIAL_MEM_
|
||||
|
||||
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
|
||||
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
|
||||
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
|
||||
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
|
||||
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
|
||||
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
|
||||
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
|
||||
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
|
||||
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
|
||||
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
|
||||
endmodule
|
||||
|
||||
module Memory(
|
||||
@@ -71,18 +105,69 @@ module Memory(
|
||||
input [31:0] io_dmem_wdata
|
||||
);
|
||||
|
||||
mem_512x32 mem_ext (
|
||||
.R0_addr (io_imem_addr[10:2]),
|
||||
wire [7:0] _mem_ext_R0_data;
|
||||
wire [7:0] _mem_ext_R1_data;
|
||||
wire [7:0] _mem_ext_R2_data;
|
||||
wire [7:0] _mem_ext_R3_data;
|
||||
wire [7:0] _mem_ext_R4_data;
|
||||
wire [7:0] _mem_ext_R5_data;
|
||||
wire [7:0] _mem_ext_R6_data;
|
||||
wire [7:0] _mem_ext_R7_data;
|
||||
wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
|
||||
wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
|
||||
wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
|
||||
mem_4096x8 mem_ext (
|
||||
.R0_addr (io_imem_addr[11:0]),
|
||||
.R0_en (1'h1),
|
||||
.R0_clk (clock),
|
||||
.R0_data (io_imem_inst),
|
||||
.R1_addr (io_dmem_addr[10:2]),
|
||||
.R0_data (_mem_ext_R0_data),
|
||||
.R1_addr (io_imem_addr[11:0] + 12'h1),
|
||||
.R1_en (1'h1),
|
||||
.R1_clk (clock),
|
||||
.R1_data (io_dmem_rdata),
|
||||
.W0_addr (io_dmem_addr[10:2]),
|
||||
.R1_data (_mem_ext_R1_data),
|
||||
.R2_addr (io_imem_addr[11:0] + 12'h2),
|
||||
.R2_en (1'h1),
|
||||
.R2_clk (clock),
|
||||
.R2_data (_mem_ext_R2_data),
|
||||
.R3_addr (io_imem_addr[11:0] + 12'h3),
|
||||
.R3_en (1'h1),
|
||||
.R3_clk (clock),
|
||||
.R3_data (_mem_ext_R3_data),
|
||||
.R4_addr (io_dmem_addr[11:0]),
|
||||
.R4_en (1'h1),
|
||||
.R4_clk (clock),
|
||||
.R4_data (_mem_ext_R4_data),
|
||||
.R5_addr (_io_dmem_rdata_T_6),
|
||||
.R5_en (1'h1),
|
||||
.R5_clk (clock),
|
||||
.R5_data (_mem_ext_R5_data),
|
||||
.R6_addr (_io_dmem_rdata_T_3),
|
||||
.R6_en (1'h1),
|
||||
.R6_clk (clock),
|
||||
.R6_data (_mem_ext_R6_data),
|
||||
.R7_addr (_io_dmem_rdata_T),
|
||||
.R7_en (1'h1),
|
||||
.R7_clk (clock),
|
||||
.R7_data (_mem_ext_R7_data),
|
||||
.W0_addr (_io_dmem_rdata_T),
|
||||
.W0_en (io_dmem_wen),
|
||||
.W0_clk (clock),
|
||||
.W0_data (io_dmem_wdata)
|
||||
.W0_data (io_dmem_wdata[31:24]),
|
||||
.W1_addr (_io_dmem_rdata_T_3),
|
||||
.W1_en (io_dmem_wen),
|
||||
.W1_clk (clock),
|
||||
.W1_data (io_dmem_wdata[23:16]),
|
||||
.W2_addr (_io_dmem_rdata_T_6),
|
||||
.W2_en (io_dmem_wen),
|
||||
.W2_clk (clock),
|
||||
.W2_data (io_dmem_wdata[15:8]),
|
||||
.W3_addr (io_dmem_addr[11:0]),
|
||||
.W3_en (io_dmem_wen),
|
||||
.W3_clk (clock),
|
||||
.W3_data (io_dmem_wdata[7:0])
|
||||
);
|
||||
assign io_imem_inst =
|
||||
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
|
||||
assign io_dmem_rdata =
|
||||
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
|
||||
endmodule
|
||||
|
||||
54
Regfile.sv
54
Regfile.sv
@@ -1,25 +1,23 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/12/28 11:28:52
|
||||
// Design Name:
|
||||
// Design Name:
|
||||
// Module Name: Regfile
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module regfile_32x32(
|
||||
input [4:0] R0_addr,
|
||||
input R0_en,
|
||||
@@ -32,27 +30,25 @@ module regfile_32x32(
|
||||
input [4:0] W0_addr,
|
||||
input W0_en,
|
||||
W0_clk,
|
||||
output [3:0] io_anodes,
|
||||
output [6:0] io_segments,
|
||||
input [31:0] W0_data
|
||||
);
|
||||
|
||||
reg [31:0] Memory[0:31];
|
||||
reg _R0_en_d0;
|
||||
reg [4:0] _R0_addr_d0;
|
||||
always @(posedge R0_clk) begin
|
||||
_R0_en_d0 <= R0_en;
|
||||
_R0_addr_d0 <= R0_addr;
|
||||
end // always @(posedge)
|
||||
reg _R1_en_d0;
|
||||
reg [4:0] _R1_addr_d0;
|
||||
always @(posedge R1_clk) begin
|
||||
_R1_en_d0 <= R1_en;
|
||||
_R1_addr_d0 <= R1_addr;
|
||||
end // always @(posedge)
|
||||
always @(posedge W0_clk) begin
|
||||
if (W0_en & 1'h1)
|
||||
Memory[W0_addr] <= W0_data;
|
||||
end // always @(posedge)
|
||||
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
|
||||
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
|
||||
|
||||
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
|
||||
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
|
||||
wire [31:0] reg16_value = Memory[16];
|
||||
DynamicDisplay display (
|
||||
.clock (W0_clk),
|
||||
.reset (1'b0),
|
||||
.reg_result (reg16_value),
|
||||
.io_anodes (io_anodes),
|
||||
.io_segments (io_segments)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
44
Top.sv
44
Top.sv
@@ -1,31 +1,30 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/12/28 11:25:38
|
||||
// Design Name:
|
||||
// Design Name:
|
||||
// Module Name: Core
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Top(
|
||||
input clock,
|
||||
reset,
|
||||
output io_exit,
|
||||
output [3:0] io_anodes, // 新增：七段显示器的阳极控制信号
|
||||
output [6:0] io_segments // 新增：七段显示器的段控制信号
|
||||
output [3:0] io_anodes,
|
||||
output [6:0] io_segments
|
||||
);
|
||||
|
||||
wire [31:0] _memory_io_imem_inst;
|
||||
@@ -34,7 +33,6 @@ module Top(
|
||||
wire [31:0] _core_io_dmem_addr;
|
||||
wire _core_io_dmem_wen;
|
||||
wire [31:0] _core_io_dmem_wdata;
|
||||
wire [31:0] _core_s0_value;
|
||||
Core core (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
@@ -44,8 +42,9 @@ module Top(
|
||||
.io_dmem_rdata (_memory_io_dmem_rdata),
|
||||
.io_dmem_wen (_core_io_dmem_wen),
|
||||
.io_dmem_wdata (_core_io_dmem_wdata),
|
||||
.io_exit (io_exit),
|
||||
.s0_value (_core_s0_value)
|
||||
.io_anodes (io_anodes),
|
||||
.io_segments (io_segments),
|
||||
.io_exit (io_exit)
|
||||
);
|
||||
Memory memory (
|
||||
.clock (clock),
|
||||
@@ -56,13 +55,4 @@ module Top(
|
||||
.io_dmem_wen (_core_io_dmem_wen),
|
||||
.io_dmem_wdata (_core_io_dmem_wdata)
|
||||
);
|
||||
// 实例化 DynamicDisplay 模块
|
||||
DynamicDisplay display (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.reg_result (_core_s0_value), // 连接 $s0 的值
|
||||
.io_anodes (io_anodes), // 连接七段显示器的阳极控制信号
|
||||
.io_segments(io_segments) // 连接七段显示器的段控制信号
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
605
TopOrigin.sv
605
TopOrigin.sv
@@ -1,15 +1,4 @@
|
||||
// Generated by CIRCT firtool-1.62.0
|
||||
// Standard header to adapt well known macros for prints and assertions.
|
||||
|
||||
// Users can define 'PRINTF_COND' to add an extra gate to prints.
|
||||
`ifndef PRINTF_COND_
|
||||
`ifdef PRINTF_COND
|
||||
`define PRINTF_COND_ (`PRINTF_COND)
|
||||
`else // PRINTF_COND
|
||||
`define PRINTF_COND_ 1
|
||||
`endif // PRINTF_COND
|
||||
`endif // not def PRINTF_COND_
|
||||
|
||||
// VCS coverage exclude_file
|
||||
module regfile_32x32(
|
||||
input [4:0] R0_addr,
|
||||
@@ -47,239 +36,395 @@ module Core(
|
||||
output io_exit
|
||||
);
|
||||
|
||||
wire exe_jmp_flg;
|
||||
wire exe_br_flg;
|
||||
wire [31:0] _regfile_ext_R0_data;
|
||||
wire [31:0] _regfile_ext_R1_data;
|
||||
reg [31:0] pc_reg;
|
||||
wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
|
||||
wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]};
|
||||
wire jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8;
|
||||
wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0;
|
||||
wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0;
|
||||
wire _csignals_T_1 = io_imem_inst[31:26] == 6'h23;
|
||||
wire _csignals_T_3 = io_imem_inst[31:26] == 6'h2B;
|
||||
wire _csignals_T_5 = _GEN == 12'h20;
|
||||
wire _csignals_T_7 = io_imem_inst[31:26] == 6'h8;
|
||||
wire _csignals_T_9 = _GEN == 12'h22;
|
||||
wire _csignals_T_11 = _GEN == 12'h24;
|
||||
wire _csignals_T_13 = _GEN == 12'h25;
|
||||
wire _csignals_T_15 = _GEN == 12'h26;
|
||||
wire _csignals_T_17 = io_imem_inst[31:26] == 6'hC;
|
||||
wire _csignals_T_19 = io_imem_inst[31:26] == 6'hD;
|
||||
wire _csignals_T_21 = _GEN == 12'h2A;
|
||||
wire _csignals_T_23 = io_imem_inst[31:26] == 6'h4;
|
||||
wire _csignals_T_25 = io_imem_inst[31:26] == 6'h5;
|
||||
wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]};
|
||||
wire _csignals_T_27 = _GEN_0 == 17'h0;
|
||||
wire _csignals_T_29 = _GEN_0 == 17'h2;
|
||||
wire _csignals_T_31 = _GEN_0 == 17'h3;
|
||||
wire _csignals_T_33 = io_imem_inst[31:26] == 6'h3;
|
||||
wire _csignals_T_35 = _GEN == 12'h8;
|
||||
wire [4:0] csignals_0 =
|
||||
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7
|
||||
? 5'h1
|
||||
: _csignals_T_9
|
||||
? 5'h2
|
||||
: _csignals_T_11
|
||||
? 5'h3
|
||||
: _csignals_T_13
|
||||
? 5'h4
|
||||
: _csignals_T_15
|
||||
? 5'h5
|
||||
: _csignals_T_17
|
||||
? 5'h3
|
||||
: _csignals_T_19
|
||||
? 5'h4
|
||||
: _csignals_T_21
|
||||
? 5'h9
|
||||
: _csignals_T_23
|
||||
? 5'hB
|
||||
: _csignals_T_25
|
||||
? 5'hC
|
||||
: _csignals_T_27
|
||||
? 5'h6
|
||||
: _csignals_T_29
|
||||
? 5'h7
|
||||
: _csignals_T_31
|
||||
? 5'h8
|
||||
: _csignals_T_33
|
||||
? 5'h1
|
||||
: _csignals_T_35 ? 5'hD : 5'h0;
|
||||
wire _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
|
||||
wire _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1;
|
||||
wire [1:0] csignals_1 =
|
||||
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
|
||||
| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19
|
||||
| _GEN_2 | ~_csignals_T_33
|
||||
? 2'h1
|
||||
: 2'h2;
|
||||
wire [2:0] csignals_2 =
|
||||
_csignals_T_1 | _csignals_T_3
|
||||
? 3'h2
|
||||
: _csignals_T_5
|
||||
? 3'h1
|
||||
: _csignals_T_7
|
||||
? 3'h2
|
||||
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
|
||||
? 3'h1
|
||||
: _csignals_T_17 | _csignals_T_19
|
||||
? 3'h2
|
||||
: _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
|
||||
wire _GEN_3 = _csignals_T_23 | _csignals_T_25;
|
||||
wire _GEN_4 =
|
||||
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
||||
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
|
||||
wire [1:0] csignals_4 =
|
||||
_csignals_T_1
|
||||
? 2'h1
|
||||
: _csignals_T_3
|
||||
? 2'h0
|
||||
: _GEN_4
|
||||
? 2'h1
|
||||
: _GEN_3
|
||||
? 2'h0
|
||||
: {1'h0,
|
||||
_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
|
||||
wire [2:0] csignals_5 =
|
||||
_csignals_T_1
|
||||
? 3'h2
|
||||
: _csignals_T_3
|
||||
? 3'h0
|
||||
: _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0;
|
||||
wire _op1_data_T = csignals_1 == 2'h1;
|
||||
wire _op1_data_T_1 = csignals_1 == 2'h2;
|
||||
wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
|
||||
wire [31:0] op2_data =
|
||||
csignals_2 == 3'h1
|
||||
? rt_data
|
||||
: csignals_2 == 3'h2
|
||||
? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
|
||||
: csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
|
||||
wire _alu_out_T = csignals_0 == 5'h1;
|
||||
wire [31:0] _alu_out_T_1 = op1_data + op2_data;
|
||||
wire _alu_out_T_3 = csignals_0 == 5'h2;
|
||||
wire [31:0] _alu_out_T_4 = op1_data - op2_data;
|
||||
wire _alu_out_T_6 = csignals_0 == 5'h3;
|
||||
wire [31:0] _alu_out_T_7 = op1_data & op2_data;
|
||||
wire _alu_out_T_8 = csignals_0 == 5'h4;
|
||||
wire [31:0] _alu_out_T_9 = op1_data | op2_data;
|
||||
wire _alu_out_T_10 = csignals_0 == 5'h5;
|
||||
wire [31:0] _alu_out_T_11 = op1_data ^ op2_data;
|
||||
wire _alu_out_T_12 = csignals_0 == 5'h6;
|
||||
wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
|
||||
wire _alu_out_T_16 = csignals_0 == 5'h7;
|
||||
wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]};
|
||||
wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5;
|
||||
wire _alu_out_T_19 = csignals_0 == 5'h8;
|
||||
wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5);
|
||||
wire _alu_out_T_24 = csignals_0 == 5'h9;
|
||||
wire _alu_out_T_28 = csignals_0 == 5'hD;
|
||||
wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)};
|
||||
wire [31:0] alu_out =
|
||||
_alu_out_T
|
||||
? _alu_out_T_1
|
||||
: _alu_out_T_3
|
||||
? _alu_out_T_4
|
||||
: _alu_out_T_6
|
||||
? _alu_out_T_7
|
||||
: _alu_out_T_8
|
||||
? _alu_out_T_9
|
||||
: _alu_out_T_10
|
||||
? _alu_out_T_11
|
||||
: _alu_out_T_12
|
||||
? _alu_out_T_14[31:0]
|
||||
: _alu_out_T_16
|
||||
? _alu_out_T_18
|
||||
: _alu_out_T_19
|
||||
? _alu_out_T_22
|
||||
: _alu_out_T_24
|
||||
? _GEN_6
|
||||
: _alu_out_T_28 ? op1_data : 32'h0;
|
||||
wire _br_flg_T_3 = op1_data == op2_data;
|
||||
wire br_flg =
|
||||
csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
|
||||
wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
|
||||
wire [31:0] wb_data =
|
||||
csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out;
|
||||
wire [4:0] wb_addr =
|
||||
csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0
|
||||
? io_imem_inst[15:11]
|
||||
: io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16];
|
||||
`ifndef SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if ((`PRINTF_COND_) & ~reset) begin
|
||||
$fwrite(32'h80000002, "---------------\n");
|
||||
$fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst);
|
||||
$fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst);
|
||||
$fwrite(32'h80000002, "pc_next: 0x%x\n",
|
||||
br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
|
||||
$fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0);
|
||||
$fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
|
||||
$fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]);
|
||||
$fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
|
||||
$fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data);
|
||||
$fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4);
|
||||
$fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
|
||||
$fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data);
|
||||
$fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
|
||||
$fwrite(32'h80000002, "---------------\n");
|
||||
end
|
||||
end // always @(posedge)
|
||||
`endif // not def SYNTHESIS
|
||||
reg [31:0] id_reg_pc;
|
||||
reg [31:0] id_reg_inst;
|
||||
reg [31:0] exe_reg_pc;
|
||||
reg [4:0] exe_reg_wb_addr;
|
||||
reg [31:0] exe_reg_op1_data;
|
||||
reg [31:0] exe_reg_op2_data;
|
||||
reg [31:0] exe_reg_rt_data;
|
||||
reg [4:0] exe_reg_exe_fun;
|
||||
reg [1:0] exe_reg_mem_wen;
|
||||
reg [1:0] exe_reg_rf_wen;
|
||||
reg [2:0] exe_reg_wb_sel;
|
||||
reg [31:0] exe_reg_imm_i_sext;
|
||||
reg [31:0] mem_reg_pc;
|
||||
reg [4:0] mem_reg_wb_addr;
|
||||
reg [31:0] mem_reg_rt_data;
|
||||
reg [1:0] mem_reg_mem_wen;
|
||||
reg [1:0] mem_reg_rf_wen;
|
||||
reg [2:0] mem_reg_wb_sel;
|
||||
reg [31:0] mem_reg_alu_out;
|
||||
reg [4:0] wb_reg_wb_addr;
|
||||
reg [1:0] wb_reg_rf_wen;
|
||||
reg [31:0] wb_reg_wb_data;
|
||||
reg [31:0] if_reg_pc;
|
||||
wire _id_inst_T = exe_br_flg | exe_jmp_flg;
|
||||
wire _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
|
||||
wire stall_flg =
|
||||
_id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
|
||||
| _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
|
||||
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
|
||||
wire _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
|
||||
wire _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
|
||||
wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
|
||||
wire _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
|
||||
wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
|
||||
wire _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
|
||||
wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
|
||||
wire _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
|
||||
wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
|
||||
wire _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
|
||||
wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
|
||||
wire _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
|
||||
wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
|
||||
wire _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
|
||||
wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
|
||||
wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
|
||||
wire _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
|
||||
wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
|
||||
wire _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
|
||||
wire _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
|
||||
wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
|
||||
wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
|
||||
wire [31:0] exe_alu_out =
|
||||
_exe_alu_out_T
|
||||
? _exe_alu_out_T_1
|
||||
: _exe_alu_out_T_3
|
||||
? _exe_alu_out_T_4
|
||||
: _exe_alu_out_T_6
|
||||
? _exe_alu_out_T_7
|
||||
: _exe_alu_out_T_8
|
||||
? _exe_alu_out_T_9
|
||||
: _exe_alu_out_T_10
|
||||
? _exe_alu_out_T_11
|
||||
: _exe_alu_out_T_12
|
||||
? _exe_alu_out_T_14[31:0]
|
||||
: _exe_alu_out_T_16
|
||||
? _exe_alu_out_T_18
|
||||
: _exe_alu_out_T_19
|
||||
? _exe_alu_out_T_22
|
||||
: _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
|
||||
assign exe_br_flg =
|
||||
exe_reg_exe_fun == 5'hB
|
||||
? exe_reg_op1_data == exe_reg_op2_data
|
||||
: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
|
||||
assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
|
||||
wire [31:0] mem_wb_data =
|
||||
mem_reg_wb_sel == 3'h2
|
||||
? io_dmem_rdata
|
||||
: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
|
||||
always @(posedge clock) begin
|
||||
if (reset)
|
||||
pc_reg <= 32'h0;
|
||||
else if (br_flg)
|
||||
pc_reg <= br_target;
|
||||
else if (jmp_flg) begin
|
||||
if (_alu_out_T)
|
||||
pc_reg <= _alu_out_T_1;
|
||||
else if (_alu_out_T_3)
|
||||
pc_reg <= _alu_out_T_4;
|
||||
else if (_alu_out_T_6)
|
||||
pc_reg <= _alu_out_T_7;
|
||||
else if (_alu_out_T_8)
|
||||
pc_reg <= _alu_out_T_9;
|
||||
else if (_alu_out_T_10)
|
||||
pc_reg <= _alu_out_T_11;
|
||||
else if (_alu_out_T_12)
|
||||
pc_reg <= _alu_out_T_14[31:0];
|
||||
else if (_alu_out_T_16)
|
||||
pc_reg <= _alu_out_T_18;
|
||||
else if (_alu_out_T_19)
|
||||
pc_reg <= _alu_out_T_22;
|
||||
else if (_alu_out_T_24)
|
||||
pc_reg <= _GEN_6;
|
||||
else if (_alu_out_T_28) begin
|
||||
if (_op1_data_T)
|
||||
pc_reg <= rs_data;
|
||||
else if (~_op1_data_T_1)
|
||||
pc_reg <= 32'h0;
|
||||
end
|
||||
else
|
||||
pc_reg <= 32'h0;
|
||||
if (reset) begin
|
||||
id_reg_pc <= 32'h0;
|
||||
id_reg_inst <= 32'h0;
|
||||
exe_reg_pc <= 32'h0;
|
||||
exe_reg_wb_addr <= 5'h0;
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
exe_reg_op2_data <= 32'h0;
|
||||
exe_reg_rt_data <= 32'h0;
|
||||
exe_reg_exe_fun <= 5'h0;
|
||||
exe_reg_mem_wen <= 2'h0;
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
exe_reg_imm_i_sext <= 32'h0;
|
||||
mem_reg_pc <= 32'h0;
|
||||
mem_reg_wb_addr <= 5'h0;
|
||||
mem_reg_rt_data <= 32'h0;
|
||||
mem_reg_mem_wen <= 2'h0;
|
||||
mem_reg_rf_wen <= 2'h0;
|
||||
mem_reg_wb_sel <= 3'h0;
|
||||
mem_reg_alu_out <= 32'h0;
|
||||
wb_reg_wb_addr <= 5'h0;
|
||||
wb_reg_rf_wen <= 2'h0;
|
||||
wb_reg_wb_data <= 32'h0;
|
||||
if_reg_pc <= 32'h0;
|
||||
end
|
||||
else begin
|
||||
automatic logic _id_rt_data_T_5;
|
||||
automatic logic _id_rt_data_T;
|
||||
automatic logic _id_rt_data_T_3;
|
||||
automatic logic _id_rt_data_T_6;
|
||||
automatic logic _id_rt_data_T_9;
|
||||
automatic logic [31:0] id_imm_i_sext;
|
||||
automatic logic _csignals_T_1 = id_inst[31:26] == 6'h23;
|
||||
automatic logic _csignals_T_3;
|
||||
automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
|
||||
automatic logic _csignals_T_5 = _GEN_1 == 12'h20;
|
||||
automatic logic _csignals_T_7 = id_inst[31:26] == 6'h8;
|
||||
automatic logic _csignals_T_9;
|
||||
automatic logic _csignals_T_11;
|
||||
automatic logic _csignals_T_13;
|
||||
automatic logic _csignals_T_15;
|
||||
automatic logic _csignals_T_17;
|
||||
automatic logic _csignals_T_19;
|
||||
automatic logic _csignals_T_21;
|
||||
automatic logic _csignals_T_23;
|
||||
automatic logic _csignals_T_25;
|
||||
automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
|
||||
automatic logic _csignals_T_27;
|
||||
automatic logic _csignals_T_29;
|
||||
automatic logic _csignals_T_31;
|
||||
automatic logic _csignals_T_33;
|
||||
automatic logic _csignals_T_35;
|
||||
automatic logic _GEN_3;
|
||||
automatic logic _GEN_4;
|
||||
automatic logic [1:0] csignals_1;
|
||||
automatic logic [2:0] csignals_2;
|
||||
automatic logic _GEN_5;
|
||||
automatic logic _GEN_6;
|
||||
_id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
|
||||
_id_rt_data_T = id_inst[20:16] == 5'h0;
|
||||
_id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
|
||||
_id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
|
||||
_id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
|
||||
id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
|
||||
_csignals_T_3 = id_inst[31:26] == 6'h2B;
|
||||
_csignals_T_9 = _GEN_1 == 12'h22;
|
||||
_csignals_T_11 = _GEN_1 == 12'h24;
|
||||
_csignals_T_13 = _GEN_1 == 12'h25;
|
||||
_csignals_T_15 = _GEN_1 == 12'h26;
|
||||
_csignals_T_17 = id_inst[31:26] == 6'hC;
|
||||
_csignals_T_19 = id_inst[31:26] == 6'hD;
|
||||
_csignals_T_21 = _GEN_1 == 12'h2A;
|
||||
_csignals_T_23 = id_inst[31:26] == 6'h4;
|
||||
_csignals_T_25 = id_inst[31:26] == 6'h5;
|
||||
_csignals_T_27 = _GEN_2 == 17'h0;
|
||||
_csignals_T_29 = _GEN_2 == 17'h2;
|
||||
_csignals_T_31 = _GEN_2 == 17'h3;
|
||||
_csignals_T_33 = id_inst[31:26] == 6'h3;
|
||||
_csignals_T_35 = _GEN_1 == 12'h8;
|
||||
_GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
|
||||
_GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
|
||||
csignals_1 =
|
||||
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
|
||||
| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
|
||||
| _csignals_T_19 | _GEN_4 | ~_csignals_T_33
|
||||
? 2'h1
|
||||
: 2'h2;
|
||||
csignals_2 =
|
||||
_csignals_T_1 | _csignals_T_3
|
||||
? 3'h2
|
||||
: _csignals_T_5
|
||||
? 3'h1
|
||||
: _csignals_T_7
|
||||
? 3'h2
|
||||
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
|
||||
? 3'h1
|
||||
: _csignals_T_17 | _csignals_T_19
|
||||
? 3'h2
|
||||
: _GEN_4
|
||||
? 3'h1
|
||||
: _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
|
||||
_GEN_5 = _csignals_T_23 | _csignals_T_25;
|
||||
_GEN_6 =
|
||||
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
||||
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
|
||||
if (~stall_flg)
|
||||
id_reg_pc <= if_reg_pc;
|
||||
if (_id_inst_T)
|
||||
id_reg_inst <= 32'h20000000;
|
||||
else if (~stall_flg)
|
||||
id_reg_inst <= io_imem_inst;
|
||||
exe_reg_pc <= id_reg_pc;
|
||||
if ((_csignals_T_1
|
||||
? 3'h2
|
||||
: _csignals_T_3
|
||||
? 3'h0
|
||||
: _GEN_6
|
||||
? 3'h1
|
||||
: _GEN_5
|
||||
? 3'h0
|
||||
: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
|
||||
& id_inst[31:26] == 6'h0)
|
||||
exe_reg_wb_addr <= id_inst[15:11];
|
||||
else if (id_inst[31:26] == 6'h3)
|
||||
exe_reg_wb_addr <= 5'h1F;
|
||||
else
|
||||
exe_reg_wb_addr <= id_inst[20:16];
|
||||
if (csignals_1 == 2'h1) begin
|
||||
if (id_inst[25:21] == 5'h0)
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
|
||||
if (_exe_alu_out_T)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_1;
|
||||
else if (_exe_alu_out_T_3)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_4;
|
||||
else if (_exe_alu_out_T_6)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_7;
|
||||
else if (_exe_alu_out_T_8)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_9;
|
||||
else if (_exe_alu_out_T_10)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_11;
|
||||
else if (_exe_alu_out_T_12)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
|
||||
else if (_exe_alu_out_T_16)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_18;
|
||||
else if (_exe_alu_out_T_19)
|
||||
exe_reg_op1_data <= _exe_alu_out_T_22;
|
||||
else if (_exe_alu_out_T_24)
|
||||
exe_reg_op1_data <= _GEN_0;
|
||||
else if (~_exe_alu_out_T_28)
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
end
|
||||
else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
|
||||
exe_reg_op1_data <= mem_wb_data;
|
||||
else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
|
||||
exe_reg_op1_data <= wb_reg_wb_data;
|
||||
else
|
||||
exe_reg_op1_data <= _regfile_ext_R1_data;
|
||||
end
|
||||
else if (csignals_1 == 2'h2)
|
||||
exe_reg_op1_data <= id_reg_pc;
|
||||
else
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
if (csignals_2 == 3'h1) begin
|
||||
if (_id_rt_data_T)
|
||||
exe_reg_op2_data <= 32'h0;
|
||||
else if (_id_rt_data_T_3) begin
|
||||
if (_exe_alu_out_T)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_1;
|
||||
else if (_exe_alu_out_T_3)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_4;
|
||||
else if (_exe_alu_out_T_6)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_7;
|
||||
else if (_exe_alu_out_T_8)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_9;
|
||||
else if (_exe_alu_out_T_10)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_11;
|
||||
else if (_exe_alu_out_T_12)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
|
||||
else if (_exe_alu_out_T_16)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_18;
|
||||
else if (_exe_alu_out_T_19)
|
||||
exe_reg_op2_data <= _exe_alu_out_T_22;
|
||||
else if (_exe_alu_out_T_24)
|
||||
exe_reg_op2_data <= _GEN_0;
|
||||
else
|
||||
exe_reg_op2_data <= _exe_alu_out_T_29;
|
||||
end
|
||||
else if (_id_rt_data_T_6)
|
||||
exe_reg_op2_data <= mem_wb_data;
|
||||
else if (_id_rt_data_T_9)
|
||||
exe_reg_op2_data <= wb_reg_wb_data;
|
||||
else
|
||||
exe_reg_op2_data <= _regfile_ext_R0_data;
|
||||
end
|
||||
else if (csignals_2 == 3'h2)
|
||||
exe_reg_op2_data <= id_imm_i_sext;
|
||||
else if (csignals_2 == 3'h4)
|
||||
exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
|
||||
else
|
||||
exe_reg_op2_data <= 32'h0;
|
||||
exe_reg_rt_data <=
|
||||
_id_rt_data_T
|
||||
? 32'h0
|
||||
: _id_rt_data_T_3
|
||||
? exe_alu_out
|
||||
: _id_rt_data_T_6
|
||||
? mem_wb_data
|
||||
: _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
|
||||
if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_9)
|
||||
exe_reg_exe_fun <= 5'h2;
|
||||
else if (_csignals_T_11)
|
||||
exe_reg_exe_fun <= 5'h3;
|
||||
else if (_csignals_T_13)
|
||||
exe_reg_exe_fun <= 5'h4;
|
||||
else if (_csignals_T_15)
|
||||
exe_reg_exe_fun <= 5'h5;
|
||||
else if (_csignals_T_17)
|
||||
exe_reg_exe_fun <= 5'h3;
|
||||
else if (_csignals_T_19)
|
||||
exe_reg_exe_fun <= 5'h4;
|
||||
else if (_csignals_T_21)
|
||||
exe_reg_exe_fun <= 5'h9;
|
||||
else if (_csignals_T_23)
|
||||
exe_reg_exe_fun <= 5'hB;
|
||||
else if (_csignals_T_25)
|
||||
exe_reg_exe_fun <= 5'hC;
|
||||
else if (_csignals_T_27)
|
||||
exe_reg_exe_fun <= 5'h6;
|
||||
else if (_csignals_T_29)
|
||||
exe_reg_exe_fun <= 5'h7;
|
||||
else if (_csignals_T_31)
|
||||
exe_reg_exe_fun <= 5'h8;
|
||||
else if (_csignals_T_33)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_35)
|
||||
exe_reg_exe_fun <= 5'hD;
|
||||
else
|
||||
exe_reg_exe_fun <= 5'h0;
|
||||
exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
|
||||
if (_csignals_T_1) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h2;
|
||||
end
|
||||
else if (_csignals_T_3) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else if (_GEN_6) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
end
|
||||
else if (_GEN_5) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else begin
|
||||
exe_reg_rf_wen <=
|
||||
{1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
|
||||
if (_GEN_3)
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
else if (_csignals_T_33)
|
||||
exe_reg_wb_sel <= 3'h3;
|
||||
else
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
exe_reg_imm_i_sext <= id_imm_i_sext;
|
||||
mem_reg_pc <= exe_reg_pc;
|
||||
mem_reg_wb_addr <= exe_reg_wb_addr;
|
||||
mem_reg_rt_data <= exe_reg_rt_data;
|
||||
mem_reg_mem_wen <= exe_reg_mem_wen;
|
||||
mem_reg_rf_wen <= exe_reg_rf_wen;
|
||||
mem_reg_wb_sel <= exe_reg_wb_sel;
|
||||
mem_reg_alu_out <= exe_alu_out;
|
||||
wb_reg_wb_addr <= mem_reg_wb_addr;
|
||||
wb_reg_rf_wen <= mem_reg_rf_wen;
|
||||
wb_reg_wb_data <= mem_wb_data;
|
||||
if (exe_br_flg)
|
||||
if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
|
||||
else if (exe_jmp_flg)
|
||||
if_reg_pc <= exe_alu_out;
|
||||
else if (~stall_flg)
|
||||
if_reg_pc <= if_reg_pc + 32'h4;
|
||||
end
|
||||
else
|
||||
pc_reg <= _pc_plus4_T;
|
||||
end // always @(posedge)
|
||||
regfile_32x32 regfile_ext (
|
||||
.R0_addr (io_imem_inst[25:21]),
|
||||
.R0_addr (id_inst[20:16]),
|
||||
.R0_en (1'h1),
|
||||
.R0_clk (clock),
|
||||
.R0_data (_regfile_ext_R0_data),
|
||||
.R1_addr (io_imem_inst[20:16]),
|
||||
.R1_addr (id_inst[25:21]),
|
||||
.R1_en (1'h1),
|
||||
.R1_clk (clock),
|
||||
.R1_data (_regfile_ext_R1_data),
|
||||
.W0_addr (wb_addr),
|
||||
.W0_en (csignals_4 == 2'h1 & (|wb_addr)),
|
||||
.W0_addr (wb_reg_wb_addr),
|
||||
.W0_en (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
|
||||
.W0_clk (clock),
|
||||
.W0_data (wb_data)
|
||||
.W0_data (wb_reg_wb_data)
|
||||
);
|
||||
assign io_imem_addr = pc_reg;
|
||||
assign io_dmem_addr = alu_out;
|
||||
assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3;
|
||||
assign io_dmem_wdata = rt_data;
|
||||
assign io_exit = io_imem_inst == 32'h114514;
|
||||
assign io_imem_addr = if_reg_pc;
|
||||
assign io_dmem_addr = mem_reg_alu_out;
|
||||
assign io_dmem_wen = mem_reg_mem_wen[0];
|
||||
assign io_dmem_wdata = mem_reg_rt_data;
|
||||
assign io_exit = id_reg_inst == 32'h114514;
|
||||
endmodule
|
||||
|
||||
// VCS coverage exclude_file
|
||||
|
||||
8
project/project/metals.sbt
Executable file
8
project/project/metals.sbt
Executable file
@@ -0,0 +1,8 @@
|
||||
// format: off
|
||||
// DO NOT EDIT! This file is auto-generated.
|
||||
|
||||
// This file enables sbt-bloop to create bloop config files.
|
||||
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
|
||||
|
||||
// format: on
|
||||
8
project/project/project/metals.sbt
Executable file
8
project/project/project/metals.sbt
Executable file
@@ -0,0 +1,8 @@
|
||||
// format: off
|
||||
// DO NOT EDIT! This file is auto-generated.
|
||||
|
||||
// This file enables sbt-bloop to create bloop config files.
|
||||
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
|
||||
|
||||
// format: on
|
||||
1
project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource
Executable file
1
project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource
Executable file
@@ -0,0 +1 @@
|
||||
[[{},{}],{}]
|
||||
@@ -0,0 +1 @@
|
||||
-1633561639
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1 @@
|
||||
644413116
|
||||
@@ -0,0 +1 @@
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
@@ -0,0 +1,3 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")[0m
|
||||
@@ -0,0 +1 @@
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
@@ -0,0 +1 @@
|
||||
[]
|
||||
@@ -0,0 +1,6 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
||||
@@ -0,0 +1,2 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,5 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
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project/target/config-classes/$87709882d327edfdfbe4.cache → project/project/target/config-classes/$c1a540d1f89b99cfe151.cache
Normal file → Executable file
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project/target/config-classes/$87709882d327edfdfbe4.cache → project/project/target/config-classes/$c1a540d1f89b99cfe151.cache
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0
project/target/config-classes/$b99baa0e80f987ddc888.cache → project/project/target/config-classes/$ce6b00de31b68d292230.cache
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0
project/target/config-classes/$b99baa0e80f987ddc888.cache → project/project/target/config-classes/$ce6b00de31b68d292230.cache
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1
project/project/target/scala-2.12/sbt-1.0/sync/copy-resource
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project/project/target/scala-2.12/sbt-1.0/sync/copy-resource
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[[{},{}],{}]
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-756073079
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project/project/target/streams/_global/_global/_global/streams/out
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||||
644413116
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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
0
project/project/target/streams/_global/ivySbt/_global/streams/out
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0
project/project/target/streams/_global/ivySbt/_global/streams/out
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3
project/project/target/streams/_global/update/_global/streams/out
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project/project/target/streams/_global/update/_global/streams/out
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@@ -0,0 +1,3 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")[0m
|
||||
@@ -0,0 +1,3 @@
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||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")[0m
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[0m[[0m[0mdebug[0m] [0m[0mOther repositories:[0m
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[0m[[0m[0mdebug[0m] [0m[0mDefault repositories:[0m
|
||||
@@ -0,0 +1 @@
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||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
@@ -0,0 +1 @@
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||||
[]
|
||||
4
project/project/target/streams/compile/bloopGenerate/_global/streams/out
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project/project/target/streams/compile/bloopGenerate/_global/streams/out
Executable file
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||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Classpath dependencies List()[0m
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[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Dependencies from configurations List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'[0m
|
||||
[0m[[0m[32msuccess[0m] [0m[0mGenerated .bloop/micore-build-build.json[0m
|
||||
@@ -0,0 +1 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRunning postGenerate for micore-build-build[0m
|
||||
0
project/project/target/streams/compile/compile/_global/streams/out
Executable file
0
project/project/target/streams/compile/compile/_global/streams/out
Executable file
@@ -0,0 +1,6 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
||||
2
project/project/target/streams/compile/copyResources/_global/streams/out
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2
project/project/target/streams/compile/copyResources/_global/streams/out
Executable file
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
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[0m[[0m[0mdebug[0m] [0m[0m [0m
|
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
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project/project/target/streams/compile/incOptions/_global/streams/out
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project/project/target/streams/compile/incOptions/_global/streams/out
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
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|
||||
|
||||
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project/project/target/streams/compile/scalacOptions/_global/streams/out
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Executable file
@@ -0,0 +1 @@
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
|
||||
0
project/project/target/streams/it/bloopGenerate/_global/streams/out
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0
project/project/target/streams/it/bloopGenerate/_global/streams/out
Executable file
@@ -0,0 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
@@ -0,0 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
@@ -0,0 +1 @@
|
||||
/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
@@ -0,0 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
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Reference in New Issue
Block a user