9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
104 lines
2.4 KiB
C
104 lines
2.4 KiB
C
/* cpu.h COPYRIGHT FUJITSU LIMITED 2016-2017 */
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#ifndef __HEADER_ARM64_ARCH_CPU_H
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#define __HEADER_ARM64_ARCH_CPU_H
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#ifndef __ASSEMBLY__
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#define sev() asm volatile("sev" : : : "memory")
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#define wfe() asm volatile("wfe" : : : "memory")
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#define wfi() asm volatile("wfi" : : : "memory")
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#define isb() asm volatile("isb" : : : "memory")
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#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
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#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
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#define mb() dsb(sy)
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#define rmb() dsb(ld)
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#define wmb() dsb(st)
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#define dma_rmb() dmb(oshld)
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#define dma_wmb() dmb(oshst)
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//#ifndef CONFIG_SMP
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//#else
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#define smp_mb() dmb(ish)
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#define smp_rmb() dmb(ishld)
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#define smp_wmb() dmb(ishst)
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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switch (sizeof(*p)) { \
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case 4: \
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asm volatile ("stlr %w1, %0" \
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: "=Q" (*p) : "r" (v) : "memory"); \
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break; \
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case 8: \
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asm volatile ("stlr %1, %0" \
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: "=Q" (*p) : "r" (v) : "memory"); \
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break; \
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} \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1; \
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compiletime_assert_atomic_type(*p); \
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switch (sizeof(*p)) { \
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case 4: \
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asm volatile ("ldar %w0, %1" \
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: "=r" (___p1) : "Q" (*p) : "memory"); \
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break; \
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case 8: \
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asm volatile ("ldar %0, %1" \
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: "=r" (___p1) : "Q" (*p) : "memory"); \
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break; \
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} \
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___p1; \
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})
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//#endif /*CONFIG_SMP*/
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define nop() asm volatile("nop");
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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/* @ref.impl linux-linaro/arch/arm64/include/asm/arch_timer.h::arch_counter_get_cntvct */
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#define read_tsc() \
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({ \
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unsigned long cval; \
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isb(); \
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asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); \
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cval; \
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})
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void init_tod_data(void);
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#if defined(CONFIG_HAS_NMI)
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static inline void cpu_enable_nmi(void)
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{
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asm volatile("msr daifclr, #2": : : "memory");
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}
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static inline void cpu_disable_nmi(void)
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{
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asm volatile("msr daifset, #2": : : "memory");
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}
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#else/*defined(CONFIG_HAS_NMI)*/
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static inline void cpu_enable_nmi(void)
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{
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}
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static inline void cpu_disable_nmi(void)
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{
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}
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#endif/*defined(CONFIG_HAS_NMI)*/
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#endif /* __ASSEMBLY__ */
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#endif /* !__HEADER_ARM64_ARCH_CPU_H */
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