0942bf0ce0
Parameters of dkprintf() should be evaluated even if dkprintf() is disabled. Because this enables to find expression of parameter obsolete and to avoid unnecessary compiler warnings such as "unused variable".
752 lines
17 KiB
C
752 lines
17 KiB
C
/**
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* \file cpu.c
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* License details are found in the file LICENSE.
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* \brief
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* Control CPU.
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* \author Taku Shimosawa <shimosawa@is.s.u-tokyo.ac.jp> \par
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* Copyright (C) 2011 - 2012 Taku Shimosawa
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*/
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/*
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* HISTORY
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*/
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#include <ihk/cpu.h>
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#include <ihk/debug.h>
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#include <types.h>
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#include <errno.h>
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#include <list.h>
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#include <memory.h>
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#include <string.h>
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#include <registers.h>
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#include <cpulocal.h>
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#include <march.h>
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#include <signal.h>
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#include <process.h>
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#define LAPIC_ID 0x020
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#define LAPIC_TIMER 0x320
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#define LAPIC_TIMER_INITIAL 0x380
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#define LAPIC_TIMER_CURRENT 0x390
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#define LAPIC_TIMER_DIVIDE 0x3e0
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#define LAPIC_SPURIOUS 0x0f0
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#define LAPIC_EOI 0x0b0
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#define LAPIC_ICR0 0x300
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#define LAPIC_ICR2 0x310
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#define LAPIC_ESR 0x280
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#define APIC_INT_LEVELTRIG 0x08000
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#define APIC_INT_ASSERT 0x04000
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#define APIC_ICR_BUSY 0x01000
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#define APIC_DEST_PHYSICAL 0x00000
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#define APIC_DM_FIXED 0x00000
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#define APIC_DM_NMI 0x00400
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#define APIC_DM_INIT 0x00500
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#define APIC_DM_STARTUP 0x00600
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//#define DEBUG_PRINT_CPU
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#ifdef DEBUG_PRINT_CPU
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#define dkprintf kprintf
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#else
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#define dkprintf(...) do { if (0) kprintf(__VA_ARGS__); } while (0)
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#endif
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void init_processors_local(int max_id);
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void assign_processor_id(void);
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void arch_delay(int);
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void x86_set_warm_reset(unsigned long ip, char *first_page_va);
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void x86_init_perfctr(void);
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extern int kprintf(const char *format, ...);
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static struct idt_entry{
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uint32_t desc[4];
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} idt[256] __attribute__((aligned(16)));
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static struct x86_desc_ptr idt_desc, gdt_desc;
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static uint64_t gdt[] __attribute__((aligned(16))) = {
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0, /* 0 */
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0, /* 8 */
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0, /* 16 */
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0, /* 24 */
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0x00af9b000000ffff, /* 32 : KERNEL_CS */
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0x00cf93000000ffff, /* 40 : KERNEL_DS */
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0x00affb000000ffff, /* 48 : USER_CS */
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0x00aff3000000ffff, /* 56 : USER_DS */
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0x0000890000000067, /* 64 : TSS */
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0, /* (72: TSS) */
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};
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struct tss64 tss __attribute__((aligned(16)));
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static void set_idt_entry(int idx, unsigned long addr)
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{
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idt[idx].desc[0] = (addr & 0xffff) | (KERNEL_CS << 16);
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idt[idx].desc[1] = (addr & 0xffff0000) | 0x8e00;
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idt[idx].desc[2] = (addr >> 32);
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idt[idx].desc[3] = 0;
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}
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static void set_idt_entry_trap_gate(int idx, unsigned long addr)
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{
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idt[idx].desc[0] = (addr & 0xffff) | (KERNEL_CS << 16);
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idt[idx].desc[1] = (addr & 0xffff0000) | 0xef00;
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idt[idx].desc[2] = (addr >> 32);
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idt[idx].desc[3] = 0;
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}
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extern uint64_t generic_common_handlers[];
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void reload_idt(void)
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{
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asm volatile("lidt %0" : : "m"(idt_desc) : "memory");
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}
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static struct list_head handlers[256 - 32];
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extern char page_fault[], general_protection_exception[];
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static void init_idt(void)
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{
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int i;
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idt_desc.size = sizeof(idt) - 1;
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idt_desc.address = (unsigned long)idt;
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for (i = 0; i < 256; i++) {
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if (i >= 32) {
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INIT_LIST_HEAD(&handlers[i - 32]);
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}
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set_idt_entry(i, generic_common_handlers[i]);
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}
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set_idt_entry(13, (unsigned long)general_protection_exception);
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set_idt_entry(14, (unsigned long)page_fault);
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reload_idt();
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}
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void init_fpu(void)
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{
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unsigned long reg;
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asm volatile("movq %%cr0, %0" : "=r"(reg));
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/* Unset EM and TS flag. */
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reg &= ~((1 << 2) | (1 << 3));
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/* Set MP flag */
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reg |= 1 << 1;
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asm volatile("movq %0, %%cr0" : : "r"(reg));
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#ifdef ENABLE_SSE
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asm volatile("movq %%cr4, %0" : "=r"(reg));
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/* Set OSFXSR flag. */
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reg |= (1 << 9);
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asm volatile("movq %0, %%cr4" : : "r"(reg));
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#endif
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asm volatile("finit");
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}
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void reload_gdt(struct x86_desc_ptr *gdt_ptr)
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{
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asm volatile("pushq %1\n"
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"leaq 1f(%%rip), %%rbx\n"
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"pushq %%rbx\n"
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"lgdt %0\n"
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"lretq\n"
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"1:\n" : :
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"m" (*gdt_ptr),
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"i" (KERNEL_CS) : "rbx");
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asm volatile("movl %0, %%ds" : : "r"(KERNEL_DS));
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asm volatile("movl %0, %%ss" : : "r"(KERNEL_DS));
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/* And, set TSS */
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asm volatile("ltr %0" : : "r"((short)GLOBAL_TSS) : "memory");
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}
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void init_gdt(void)
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{
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register unsigned long stack_pointer asm("rsp");
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unsigned long tss_addr = (unsigned long)&tss;
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memset(&tss, 0, sizeof(tss));
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tss.rsp0 = stack_pointer;
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/* 0x89 = Present (8) | Type = 9 (TSS) */
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gdt[GLOBAL_TSS_ENTRY] = (sizeof(tss) - 1)
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| ((tss_addr & 0xffffff) << 16)
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| (0x89UL << 40) | ((tss_addr & 0xff000000) << 32);
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gdt[GLOBAL_TSS_ENTRY + 1] = (tss_addr >> 32);
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gdt_desc.size = sizeof(gdt) - 1;
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gdt_desc.address = (unsigned long)gdt;
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/* Load the new GDT, and set up CS, DS and SS. */
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reload_gdt(&gdt_desc);
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}
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static void *lapic_vp;
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void lapic_write(int reg, unsigned int value)
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{
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*(volatile unsigned int *)((char *)lapic_vp + reg) = value;
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}
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unsigned int lapic_read(int reg)
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{
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return *(volatile unsigned int *)((char *)lapic_vp + reg);
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}
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void lapic_icr_write(unsigned int h, unsigned int l)
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{
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lapic_write(LAPIC_ICR2, (unsigned int)h);
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lapic_write(LAPIC_ICR0, l);
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}
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void init_lapic(void)
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{
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unsigned long baseaddr;
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/* Enable Local APIC */
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baseaddr = rdmsr(MSR_IA32_APIC_BASE);
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if (!lapic_vp) {
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lapic_vp = map_fixed_area(baseaddr & PAGE_MASK, PAGE_SIZE, 1);
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}
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baseaddr |= 0x800;
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wrmsr(MSR_IA32_APIC_BASE, baseaddr);
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lapic_write(LAPIC_SPURIOUS, 0x1ff);
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}
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void lapic_ack(void)
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{
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lapic_write(LAPIC_EOI, 0);
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}
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static void set_kstack(unsigned long ptr)
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{
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struct x86_cpu_local_variables *v;
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v = get_x86_this_cpu_local();
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v->kernel_stack = ptr;
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v->tss.rsp0 = ptr;
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}
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static void init_smp_processor(void)
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{
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struct x86_cpu_local_variables *v;
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unsigned long tss_addr;
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v = get_x86_this_cpu_local();
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tss_addr = (unsigned long)&v->tss;
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v->apic_id = lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT;
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memcpy(v->gdt, gdt, sizeof(v->gdt));
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memset(&v->tss, 0, sizeof(v->tss));
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v->gdt[GLOBAL_TSS_ENTRY] = (sizeof(v->tss) - 1)
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| ((tss_addr & 0xffffff) << 16)
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| (0x89UL << 40) | ((tss_addr & 0xff000000) << 32);
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v->gdt[GLOBAL_TSS_ENTRY + 1] = (tss_addr >> 32);
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v->gdt_ptr.size = sizeof(v->gdt) - 1;
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v->gdt_ptr.address = (unsigned long)v->gdt;
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/* Load the new GDT, and set up CS, DS and SS. */
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reload_gdt(&v->gdt_ptr);
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set_kstack((unsigned long)get_x86_this_cpu_kstack());
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}
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static char *trampoline_va, *first_page_va;
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void ihk_mc_init_ap(void)
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{
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struct ihk_mc_cpu_info *cpu_info = ihk_mc_get_cpu_info();
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trampoline_va = map_fixed_area(AP_TRAMPOLINE, AP_TRAMPOLINE_SIZE,
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0);
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first_page_va = map_fixed_area(0, PAGE_SIZE, 0);
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kprintf("# of cpus : %d\n", cpu_info->ncpus);
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init_processors_local(cpu_info->ncpus);
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/* Do initialization for THIS cpu (BSP) */
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assign_processor_id();
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init_smp_processor();
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}
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extern void init_page_table(void);
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extern char x86_syscall[];
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long (*__x86_syscall_handler)(int, ihk_mc_user_context_t *);
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void init_syscall(void)
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{
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unsigned long r;
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r = rdmsr(MSR_EFER);
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r |= 1; /* SYSCALL Enable */
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wrmsr(MSR_EFER, r);
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r = (((unsigned long)KERNEL_CS) << 32)
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| (((unsigned long)USER_CS) << 48);
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wrmsr(MSR_STAR, r);
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wrmsr(MSR_LSTAR, (unsigned long)x86_syscall);
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}
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static void enable_page_protection_fault(void)
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{
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asm volatile (
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"pushf ;"
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"cli ;"
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"mov %%cr0,%%rax;"
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"or $0x10000,%%rax;"
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"mov %%rax,%%cr0;"
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"popf"
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::: "%rax");
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return;
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}
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static int no_execute_available = 0;
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static void enable_no_execute(void)
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{
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unsigned long efer;
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if (!no_execute_available) {
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return;
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}
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efer = rdmsr(MSR_EFER);
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#define IA32_EFER_NXE (1UL << 11)
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efer |= IA32_EFER_NXE;
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wrmsr(MSR_EFER, efer);
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return;
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}
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static void check_no_execute(void)
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{
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uint32_t edx;
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extern void enable_ptattr_no_execute(void);
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/* check Execute Disable Bit available bit */
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asm ("cpuid" : "=d" (edx) : "a" (0x80000001) : "%rbx", "%rcx");
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no_execute_available = (edx & (1 << 20))? 1: 0;
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kprintf("no_execute_available: %d\n", no_execute_available);
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if (no_execute_available) {
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enable_ptattr_no_execute();
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}
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return;
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}
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void init_cpu(void)
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{
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enable_page_protection_fault();
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enable_no_execute();
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init_fpu();
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init_lapic();
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init_syscall();
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x86_init_perfctr();
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}
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void setup_x86(void)
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{
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cpu_disable_interrupt();
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init_idt();
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init_gdt();
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init_page_table();
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check_no_execute();
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init_cpu();
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kprintf("setup_x86 done.\n");
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}
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static volatile int cpu_boot_status;
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void call_ap_func(void (*next_func)(void))
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{
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cpu_boot_status = 1;
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next_func();
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}
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void setup_x86_ap(void (*next_func)(void))
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{
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unsigned long rsp;
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cpu_disable_interrupt();
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assign_processor_id();
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init_smp_processor();
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reload_idt();
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init_cpu();
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rsp = (unsigned long)get_x86_this_cpu_kstack();
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asm volatile("movq %0, %%rdi\n"
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"movq %1, %%rsp\n"
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"call *%2" : : "r"(next_func), "r"(rsp), "r"(call_ap_func)
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: "rdi");
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while(1);
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}
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void arch_show_interrupt_context(const void *reg);
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void set_signal(int sig, void *regs, struct siginfo *info);
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void check_signal(unsigned long rc, void *regs);
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extern void tlb_flush_handler(int vector);
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void handle_interrupt(int vector, struct x86_regs *regs)
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{
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struct ihk_mc_interrupt_handler *h;
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lapic_ack();
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dkprintf("CPU[%d] got interrupt, vector: %d, RIP: 0x%lX\n",
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ihk_mc_get_processor_id(), vector, regs->rip);
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if (vector < 0 || vector > 255) {
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panic("Invalid interrupt vector.");
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}
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else if (vector < 32) {
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if (vector == 8 ||
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(vector >= 10 && vector <= 15) || vector == 17) {
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kprintf("Exception %d, rflags: 0x%lX CS: 0x%lX, RIP: 0x%lX\n",
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vector, regs->rflags, regs->cs, regs->rip);
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} else {
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kprintf("Exception %d, rflags: 0x%lX CS: 0x%lX, RIP: 0x%lX\n",
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vector, regs->rflags, regs->cs, regs->rip);
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}
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arch_show_interrupt_context(regs);
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panic("Unhandled exception");
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}
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else if (vector >= IHK_TLB_FLUSH_IRQ_VECTOR_START &&
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vector < IHK_TLB_FLUSH_IRQ_VECTOR_END) {
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tlb_flush_handler(vector);
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}
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else {
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list_for_each_entry(h, &handlers[vector - 32], list) {
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if (h->func) {
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h->func(h->priv);
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}
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}
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}
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check_signal(0, regs);
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check_need_resched();
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}
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void gpe_handler(struct x86_regs *regs)
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{
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struct siginfo info;
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kprintf("General protection fault (err: %lx, %lx:%lx)\n",
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regs->error, regs->cs, regs->rip);
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arch_show_interrupt_context(regs);
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memset(&info, '\0', sizeof info);
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set_signal(SIGILL, regs, &info);
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check_signal(0, regs);
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check_need_resched();
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// panic("GPF");
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}
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void x86_issue_ipi(unsigned int apicid, unsigned int low)
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{
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lapic_icr_write(apicid << LAPIC_ICR_ID_SHIFT, low);
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}
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static void outb(uint8_t v, uint16_t port)
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{
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asm volatile("outb %0, %1" : : "a" (v), "d" (port));
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}
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static void set_warm_reset_vector(unsigned long ip)
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{
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x86_set_warm_reset(ip, first_page_va);
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}
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static void wait_icr_idle(void)
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{
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while (lapic_read(LAPIC_ICR0) & APIC_ICR_BUSY) {
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cpu_pause();
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}
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}
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static void __x86_wakeup(int apicid, unsigned long ip)
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{
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int retry = 3;
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set_warm_reset_vector(ip);
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/* Clear the error */
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lapic_write(LAPIC_ESR, 0);
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lapic_read(LAPIC_ESR);
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/* INIT */
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x86_issue_ipi(apicid,
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APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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wait_icr_idle();
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x86_issue_ipi(apicid,
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APIC_INT_LEVELTRIG | APIC_DM_INIT);
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wait_icr_idle();
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while (retry--) {
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lapic_read(LAPIC_ESR);
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x86_issue_ipi(apicid, APIC_DM_STARTUP | (ip >> 12));
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wait_icr_idle();
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arch_delay(200);
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if (cpu_boot_status)
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break;
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}
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}
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/** IHK Functions **/
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void cpu_halt(void)
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{
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asm volatile("hlt");
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}
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void cpu_safe_halt(void)
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{
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asm volatile("sti; hlt");
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}
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void cpu_enable_interrupt(void)
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{
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asm volatile("sti");
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}
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void cpu_disable_interrupt(void)
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{
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asm volatile("cli");
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}
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void cpu_restore_interrupt(unsigned long flags)
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{
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asm volatile("push %0; popf" : : "g"(flags) : "memory", "cc");
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}
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void cpu_pause(void)
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{
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asm volatile("pause" ::: "memory");
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}
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unsigned long cpu_disable_interrupt_save(void)
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{
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unsigned long flags;
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asm volatile("pushf; pop %0; cli" : "=r"(flags) : : "memory", "cc");
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return flags;
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}
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int ihk_mc_register_interrupt_handler(int vector,
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struct ihk_mc_interrupt_handler *h)
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{
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if (vector < 32 || vector > 255) {
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return -EINVAL;
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}
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list_add_tail(&h->list, &handlers[vector - 32]);
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return 0;
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}
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int ihk_mc_unregister_interrupt_handler(int vector,
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struct ihk_mc_interrupt_handler *h)
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{
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list_del(&h->list);
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return 0;
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}
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extern unsigned long __page_fault_handler_address;
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void ihk_mc_set_page_fault_handler(void (*h)(void *, uint64_t, void *))
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{
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__page_fault_handler_address = (unsigned long)h;
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}
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extern char trampoline_code_data[], trampoline_code_data_end[];
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struct page_table *get_init_page_table(void);
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unsigned long get_transit_page_table(void);
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void ihk_mc_boot_cpu(int cpuid, unsigned long pc)
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{
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unsigned long *p;
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p = (unsigned long *)trampoline_va;
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memcpy(p, trampoline_code_data,
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trampoline_code_data_end - trampoline_code_data);
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p[1] = (unsigned long)virt_to_phys(get_init_page_table());
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p[2] = (unsigned long)setup_x86_ap;
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p[3] = pc;
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p[6] = (unsigned long)get_transit_page_table();
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if (!p[6]) {
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p[6] = p[1];
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}
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cpu_boot_status = 0;
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__x86_wakeup(cpuid, AP_TRAMPOLINE);
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/* XXX: Time out */
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while (!cpu_boot_status) {
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cpu_pause();
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}
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}
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void ihk_mc_init_context(ihk_mc_kernel_context_t *new_ctx,
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void *stack_pointer, void (*next_function)(void))
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{
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unsigned long *sp;
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if (!stack_pointer) {
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stack_pointer = get_x86_this_cpu_kstack();
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}
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sp = stack_pointer;
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memset(new_ctx, 0, sizeof(ihk_mc_kernel_context_t));
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/* Set the return address */
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new_ctx->rsp = (unsigned long)(sp - 1);
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sp[-1] = (unsigned long)next_function;
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}
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extern char enter_user_mode[];
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void ihk_mc_init_user_process(ihk_mc_kernel_context_t *ctx,
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ihk_mc_user_context_t **puctx,
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void *stack_pointer, unsigned long new_pc,
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unsigned long user_sp)
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{
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char *sp;
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ihk_mc_user_context_t *uctx;
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sp = stack_pointer;
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sp -= sizeof(ihk_mc_user_context_t);
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uctx = (ihk_mc_user_context_t *)sp;
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*puctx = uctx;
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memset(uctx, 0, sizeof(ihk_mc_user_context_t));
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uctx->cs = USER_CS;
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uctx->rip = new_pc;
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uctx->ss = USER_DS;
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uctx->rsp = user_sp;
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uctx->rflags = RFLAGS_IF;
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ihk_mc_init_context(ctx, sp, (void (*)(void))enter_user_mode);
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ctx->rsp0 = (unsigned long)stack_pointer;
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}
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void ihk_mc_modify_user_context(ihk_mc_user_context_t *uctx,
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enum ihk_mc_user_context_regtype reg,
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unsigned long value)
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{
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if (reg == IHK_UCR_STACK_POINTER) {
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uctx->rsp = value;
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} else if (reg == IHK_UCR_PROGRAM_COUNTER) {
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uctx->rip = value;
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}
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}
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void ihk_mc_print_user_context(ihk_mc_user_context_t *uctx)
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{
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kprintf("CS:RIP = %04lx:%16lx\n", uctx->cs, uctx->rip);
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kprintf("%16lx %16lx %16lx %16lx\n%16lx %16lx %16lx\n",
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uctx->rax, uctx->rbx, uctx->rcx, uctx->rdx,
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uctx->rsi, uctx->rdi, uctx->rsp);
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}
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void ihk_mc_set_syscall_handler(long (*handler)(int, ihk_mc_user_context_t *))
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{
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__x86_syscall_handler = handler;
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}
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void ihk_mc_delay_us(int us)
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{
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arch_delay(us);
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}
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void arch_show_interrupt_context(const void *reg)
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{
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const struct x86_regs *regs = reg;
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int irqflags;
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irqflags = kprintf_lock();
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__kprintf("CS:RIP = %4lx:%16lx\n", regs->cs, regs->rip);
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__kprintf(" RAX RBX RCX RDX\n");
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__kprintf("%16lx %16lx %16lx %16lx\n",
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regs->rax, regs->rbx, regs->rcx, regs->rdx);
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__kprintf(" RSI RDI RSP RBP\n");
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__kprintf("%16lx %16lx %16lx %16lx\n",
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regs->rsi, regs->rdi, regs->rsp, regs->rbp);
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__kprintf(" R8 R9 R10 R11\n");
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__kprintf("%16lx %16lx %16lx %16lx\n",
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regs->r8, regs->r9, regs->r10, regs->r11);
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__kprintf(" R12 R13 R14 R15\n");
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__kprintf("%16lx %16lx %16lx %16lx\n",
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regs->r12, regs->r13, regs->r14, regs->r15);
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__kprintf(" CS SS RFLAGS ERROR\n");
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__kprintf("%16lx %16lx %16lx %16lx\n",
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regs->cs, regs->ss, regs->rflags, regs->error);
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kprintf_unlock(irqflags);
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}
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int ihk_mc_arch_set_special_register(enum ihk_asr_type type,
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|
unsigned long value)
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|
{
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|
/* GS modification is not permitted */
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|
switch (type) {
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case IHK_ASR_X86_FS:
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wrmsr(MSR_FS_BASE, value);
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return 0;
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default:
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return -EINVAL;
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}
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}
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int ihk_mc_arch_get_special_register(enum ihk_asr_type type,
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|
unsigned long *value)
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|
{
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|
/* GS modification is not permitted */
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|
switch (type) {
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|
case IHK_ASR_X86_FS:
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|
*value = rdmsr(MSR_FS_BASE);
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|
return 0;
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|
default:
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|
return -EINVAL;
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|
}
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|
}
|
|
|
|
int ihk_mc_interrupt_cpu(int cpu, int vector)
|
|
{
|
|
dkprintf("[%d] ihk_mc_interrupt_cpu: %d\n", ihk_mc_get_processor_id(), cpu);
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|
|
|
wait_icr_idle();
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|
x86_issue_ipi(cpu, vector);
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|
return 0;
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|
}
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