171 lines
3.7 KiB
ArmAsm
171 lines
3.7 KiB
ArmAsm
/* sve_asm.S COPYRIGHT FUJITSU LIMITED 2016-2019 */
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.globl load_z31
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load_z31:
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.cpu cortex-a53+fp+simd+sve
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ldr z31, [x0]
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ret
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.type load_z31, @function
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.size load_z31, .-load_z31
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.globl store_z31
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store_z31:
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add z31.d, z31.d,#1
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str z31, [x0]
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ret
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.type store_z31, @function
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.size store_z31, .-store_z31
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/* void sve_save_state(void *state, unsigned int *pfpsr); */
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.globl sve_load_state
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.align 4
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sve_load_state:
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/* load z register */
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ldr z0, [x0,#-34,mul vl]
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ldr z1, [x0,#-33,mul vl]
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ldr z2, [x0,#-32,mul vl]
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ldr z3, [x0,#-31,mul vl]
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ldr z4, [x0,#-30,mul vl]
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ldr z5, [x0,#-29,mul vl]
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ldr z6, [x0,#-28,mul vl]
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ldr z7, [x0,#-27,mul vl]
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ldr z8, [x0,#-26,mul vl]
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ldr z9, [x0,#-25,mul vl]
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ldr z10, [x0,#-24,mul vl]
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ldr z11, [x0,#-23,mul vl]
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ldr z12, [x0,#-22,mul vl]
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ldr z13, [x0,#-21,mul vl]
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ldr z14, [x0,#-20,mul vl]
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ldr z15, [x0,#-19,mul vl]
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ldr z16, [x0,#-18,mul vl]
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ldr z17, [x0,#-17,mul vl]
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ldr z18, [x0,#-16,mul vl]
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ldr z19, [x0,#-15,mul vl]
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ldr z20, [x0,#-14,mul vl]
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ldr z21, [x0,#-13,mul vl]
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ldr z22, [x0,#-12,mul vl]
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ldr z23, [x0,#-11,mul vl]
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ldr z24, [x0,#-10,mul vl]
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ldr z25, [x0,#-9,mul vl]
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ldr z26, [x0,#-8,mul vl]
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ldr z27, [x0,#-7,mul vl]
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ldr z28, [x0,#-6,mul vl]
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ldr z29, [x0,#-5,mul vl]
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ldr z30, [x0,#-4,mul vl]
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ldr z31, [x0,#-3,mul vl]
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/* write ffr */
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ldr p0, [x0]
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wrffr p0.b
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/* load p register */
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ldr p0, [x0,#-16,mul vl]
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ldr p1, [x0,#-15,mul vl]
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ldr p2, [x0,#-14,mul vl]
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ldr p3, [x0,#-13,mul vl]
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ldr p4, [x0,#-12,mul vl]
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ldr p5, [x0,#-11,mul vl]
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ldr p6, [x0,#-10,mul vl]
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ldr p7, [x0,#-9,mul vl]
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ldr p8, [x0,#-8,mul vl]
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ldr p9, [x0,#-7,mul vl]
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ldr p10, [x0,#-6,mul vl]
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ldr p11, [x0,#-5,mul vl]
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ldr p12, [x0,#-4,mul vl]
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ldr p13, [x0,#-3,mul vl]
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ldr p14, [x0,#-2,mul vl]
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ldr p15, [x0,#-1,mul vl]
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/* write fpsr */
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ldr w2, [x1]
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msr fpsr, x2
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/* write fpcr */
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ldr w2, [x1,#4]
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msr fpcr, x2
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ret
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.type sve_load_state, @function
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.size sve_load_state, .-sve_load_state
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/* void sve_load_state(void const *state, unsigned int const *pfpsr); */
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.globl sve_save_state
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.align 4
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sve_save_state:
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/* store z register */
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str z0, [x0,#-34,mul vl]
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str z1, [x0,#-33,mul vl]
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str z2, [x0,#-32,mul vl]
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str z3, [x0,#-31,mul vl]
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str z4, [x0,#-30,mul vl]
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str z5, [x0,#-29,mul vl]
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str z6, [x0,#-28,mul vl]
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str z7, [x0,#-27,mul vl]
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str z8, [x0,#-26,mul vl]
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str z9, [x0,#-25,mul vl]
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str z10, [x0,#-24,mul vl]
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str z11, [x0,#-23,mul vl]
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str z12, [x0,#-22,mul vl]
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str z13, [x0,#-21,mul vl]
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str z14, [x0,#-20,mul vl]
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str z15, [x0,#-19,mul vl]
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str z16, [x0,#-18,mul vl]
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str z17, [x0,#-17,mul vl]
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str z18, [x0,#-16,mul vl]
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str z19, [x0,#-15,mul vl]
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str z20, [x0,#-14,mul vl]
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str z21, [x0,#-13,mul vl]
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str z22, [x0,#-12,mul vl]
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str z23, [x0,#-11,mul vl]
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str z24, [x0,#-10,mul vl]
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str z25, [x0,#-9,mul vl]
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str z26, [x0,#-8,mul vl]
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str z27, [x0,#-7,mul vl]
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str z28, [x0,#-6,mul vl]
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str z29, [x0,#-5,mul vl]
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str z30, [x0,#-4,mul vl]
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str z31, [x0,#-3,mul vl]
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/* store p register */
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str p0, [x0,#-16,mul vl]
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str p1, [x0,#-15,mul vl]
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str p2, [x0,#-14,mul vl]
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str p3, [x0,#-13,mul vl]
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str p4, [x0,#-12,mul vl]
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str p5, [x0,#-11,mul vl]
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str p6, [x0,#-10,mul vl]
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str p7, [x0,#-9,mul vl]
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str p8, [x0,#-8,mul vl]
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str p9, [x0,#-7,mul vl]
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str p10, [x0,#-6,mul vl]
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str p11, [x0,#-5,mul vl]
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str p12, [x0,#-4,mul vl]
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str p13, [x0,#-3,mul vl]
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str p14, [x0,#-2,mul vl]
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str p15, [x0,#-1,mul vl]
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/* read ffr */
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rdffr p0.b
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str p0, [x0]
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ldr p0, [x0,#-16,mul vl]
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/* read fpsr */
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mrs x2, fpsr
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str w2, [x1]
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/* read fpcr */
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mrs x2, fpcr
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str w2, [x1,#4]
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ret
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.type sve_save_state, @function
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.size sve_save_state, .-sve_save_state
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/* unsigned int sve_get_vl(void); */
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.globl sve_get_vl
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.align 4
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sve_get_vl:
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rdvl x0, #1
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ret
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.type sve_get_vl, @function
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.size sve_get_vl, .-sve_get_vl
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