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freeze: change freeze-thaw to normal interrupt

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Change-Id: Ib4dbac28f0074595e92ef316945b37ef4bc18327
This commit is contained in:
TOIDA,Suguru
2019-08-27 13:32:37 +09:00
committed by Masamichi Takagi
parent 299d47abf5
commit ff982b8594
8 changed files with 67 additions and 33 deletions
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31
arch/arm64/kernel/cpu.c
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@@ -119,6 +119,22 @@ static struct ihk_mc_interrupt_handler cpu_stop_handler = {
};
extern long freeze_thaw(void *nmi_ctx);
static void multi_interrupt_handler(void *priv)
{
switch (multi_intr_mode) {
case 1:
case 2: /* mode == 1or2, for FREEZER intr */
dkprintf("%s: freeze mode intr catch. (multi_intr_mode=%d)\n",
__func__, multi_intr_mode);
freeze_thaw(NULL);
break;
default:
ekprintf("%s: Unknown multi-intr-mode(%d) detected.\n",
__func__, multi_intr_mode);
break;
}
}
static void multi_nm_interrupt_handler(void *priv)
{
extern int nmi_mode;
@@ -126,14 +142,6 @@ static void multi_nm_interrupt_handler(void *priv)
union arm64_cpu_local_variables *clv;
switch (nmi_mode) {
case 1:
case 2:
/* mode == 1or2, for FREEZER NMI */
dkprintf("%s: freeze mode NMI catch. (nmi_mode=%d)\n",
__func__, nmi_mode);
freeze_thaw(NULL);
break;
case 0:
/* mode == 0, for MEMDUMP NMI */
clv = get_arm64_this_cpu_local();
@@ -164,6 +172,11 @@ static void multi_nm_interrupt_handler(void *priv)
}
}
static struct ihk_mc_interrupt_handler multi_intr_handler = {
.func = multi_interrupt_handler,
.priv = NULL,
};
static struct ihk_mc_interrupt_handler multi_nmi_handler = {
.func = multi_nm_interrupt_handler,
.priv = NULL,
@@ -428,6 +441,8 @@ void ihk_mc_init_ap(void)
ihk_mc_register_interrupt_handler(INTRID_CPU_STOP, &cpu_stop_handler);
ihk_mc_register_interrupt_handler(INTRID_MULTI_NMI, &multi_nmi_handler);
ihk_mc_register_interrupt_handler(INTRID_MULTI_INTR,
&multi_intr_handler);
ihk_mc_register_interrupt_handler(
ihk_mc_get_vector(IHK_TLB_FLUSH_IRQ_VECTOR_START),
&remote_tlb_flush_handler);

5
arch/arm64/kernel/include/irq.h
View File

@@ -1,4 +1,4 @@
/* irq.h COPYRIGHT FUJITSU LIMITED 2015-2018 */
/* irq.h COPYRIGHT FUJITSU LIMITED 2015-2019 */
#ifndef __HEADER_ARM64_IRQ_H
#define __HEADER_ARM64_IRQ_H
@@ -14,7 +14,8 @@
#define INTRID_QUERY_FREE_MEM 2
#define INTRID_CPU_STOP 3
#define INTRID_TLB_FLUSH 4
#define INTRID_STACK_TRACE 6
#define INTRID_STACK_TRACE 5
#define INTRID_MULTI_INTR 6
#define INTRID_MULTI_NMI 7
/* use PPI interrupt number */