x86 Page Attribute Table (PAT) MSR support.

Reconfigure PAT to permit write-combining memory type to be assigned
on a page-by-page basis. Changes PWT and PCD bit combinations in page
table entries so that they correspond to the following format:

  PAT
  |PCD
  ||PWT
  |||
  000 WB  Write Back (WB)
  001 WC  Write Combining (WC)
  010 UC- Uncached (UC-)
  011 UC  Uncacheable (UC)

arch/x86/kernel/include/registers.h

@@ -55,6 +55,8 @@
 #define MSR_IA32_MISC_ENABLE		0x000001a0
 #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
 #define MSR_NHM_TURBO_RATIO_LIMIT	0x000001ad
+#define MSR_IA32_CR_PAT			0x00000277
+
 
 #define CVAL(event, mask) \
         ((((event) & 0xf00) << 24) | ((mask) << 8) | ((event) & 0xff))