Following arm64-support to development branch
This includes the following fixes: * fix build of arch/arm64/kernel/vdso Change-Id: I73b05034d29f7f8731ac17f9736edbba4fb2c639
This commit is contained in:
Takehiro Shiratori
committed by
Dominique Martinet
Dominique Martinet
parent
e52d748744
commit
d4d78e9c61
@@ -1,5 +1,4 @@
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/* irq-gic-v3.c COPYRIGHT FUJITSU LIMITED 2015-2017 */
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/* irq-gic-v3.c COPYRIGHT FUJITSU LIMITED 2015-2018 */
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#include <irq.h>
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#include <arm-gic-v2.h>
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#include <arm-gic-v3.h>
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@@ -8,6 +7,8 @@
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#include <process.h>
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#include <syscall.h>
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#include <debug.h>
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#include <arch-timer.h>
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#include <cls.h>
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//#define DEBUG_GICV3
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@@ -264,6 +265,7 @@ static void arm64_raise_spi_gicv3(uint32_t cpuid, uint32_t vector)
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static void arm64_raise_lpi_gicv3(uint32_t cpuid, uint32_t vector)
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{
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// @todo.impl
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ekprintf("%s called.\n", __func__);
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}
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void arm64_issue_ipi_gicv3(uint32_t cpuid, uint32_t vector)
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@@ -281,7 +283,7 @@ void arm64_issue_ipi_gicv3(uint32_t cpuid, uint32_t vector)
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// send LPI (allow only to host)
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arm64_raise_lpi_gicv3(cpuid, vector);
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} else {
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ekprintf("#%d is bad irq number.", vector);
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ekprintf("#%d is bad irq number.\n", vector);
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}
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}
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@@ -289,10 +291,11 @@ extern int interrupt_from_user(void *);
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void handle_interrupt_gicv3(struct pt_regs *regs)
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{
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uint64_t irqnr;
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const int from_user = interrupt_from_user(regs);
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irqnr = gic_read_iar();
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cpu_enable_nmi();
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set_cputime(interrupt_from_user(regs)? 1: 2);
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set_cputime(from_user ? CPUTIME_MODE_U2K : CPUTIME_MODE_K2K_IN);
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while (irqnr != ICC_IAR1_EL1_SPURIOUS) {
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if ((irqnr < 1020) || (irqnr >= 8192)) {
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gic_write_eoir(irqnr);
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@@ -300,11 +303,51 @@ void handle_interrupt_gicv3(struct pt_regs *regs)
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}
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irqnr = gic_read_iar();
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}
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set_cputime(0);
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set_cputime(from_user ? CPUTIME_MODE_K2U : CPUTIME_MODE_K2K_OUT);
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/* for migration by IPI */
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if (get_this_cpu_local_var()->flags & CPU_FLAG_NEED_MIGRATE) {
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schedule();
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check_signal(0, regs, 0);
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}
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}
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static uint64_t gic_mpidr_to_affinity(unsigned long mpidr)
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{
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uint64_t aff;
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aff = ((uint64_t)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
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MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
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MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
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MPIDR_AFFINITY_LEVEL(mpidr, 0));
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return aff;
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}
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static void init_spi_routing(uint32_t irq, uint32_t linux_cpu)
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{
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uint64_t spi_route_reg_val, spi_route_reg_offset;
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if (irq < 32 || 1020 <= irq) {
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ekprintf("%s: irq is not spi number. (irq=%d)\n",
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__func__, irq);
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return;
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}
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/* write to GICD_IROUTER */
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spi_route_reg_offset = irq * 8;
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spi_route_reg_val = gic_mpidr_to_affinity(cpu_logical_map(linux_cpu));
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writeq_relaxed(spi_route_reg_val,
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(void *)(dist_base + GICD_IROUTER +
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spi_route_reg_offset));
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}
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void gic_dist_init_gicv3(unsigned long dist_base_pa, unsigned long size)
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{
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extern int spi_table[];
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extern int nr_spi_table;
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int i;
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dist_base = map_fixed_area(dist_base_pa, size, 1 /*non chachable*/);
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#ifdef USE_CAVIUM_THUNDER_X
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@@ -313,6 +356,14 @@ void gic_dist_init_gicv3(unsigned long dist_base_pa, unsigned long size)
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is_cavium_thunderx = 1;
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}
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#endif
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/* initialize spi routing */
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for (i = 0; i < nr_spi_table; i++) {
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if (spi_table[i] == -1) {
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continue;
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}
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init_spi_routing(spi_table[i], i);
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}
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}
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void gic_cpu_init_gicv3(unsigned long cpu_base_pa, unsigned long size)
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@@ -349,11 +400,23 @@ void gic_enable_gicv3(void)
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void *rd_sgi_base = rbase + 0x10000 /* SZ_64K */;
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int i;
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unsigned int enable_ppi_sgi = GICD_INT_EN_SET_SGI;
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extern int ihk_param_nr_pmu_irq_affi;
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extern int ihk_param_pmu_irq_affi[CONFIG_SMP_MAX_CORES];
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if (is_use_virt_timer()) {
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enable_ppi_sgi |= GICD_ENABLE << get_virt_timer_intrid();
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} else {
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enable_ppi_sgi |= GICD_ENABLE << get_phys_timer_intrid();
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enable_ppi_sgi |= GICD_ENABLE << get_timer_intrid();
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if (0 < ihk_param_nr_pmu_irq_affi) {
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for (i = 0; i < ihk_param_nr_pmu_irq_affi; i++) {
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if ((0 <= ihk_param_pmu_irq_affi[i]) &&
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(ihk_param_pmu_irq_affi[i] <
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sizeof(enable_ppi_sgi) * BITS_PER_BYTE)) {
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enable_ppi_sgi |= GICD_ENABLE <<
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ihk_param_pmu_irq_affi[i];
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}
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}
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}
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else {
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enable_ppi_sgi |= GICD_ENABLE << INTRID_PERF_OVF;
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}
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/*
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@@ -366,9 +429,10 @@ void gic_enable_gicv3(void)
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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for (i = 0; i < 32; i += 4) {
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writel_relaxed(GICD_INT_DEF_PRI_X4,
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rd_sgi_base + GIC_DIST_PRI + i * 4 / 4);
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rd_sgi_base + GIC_DIST_PRI + i);
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}
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/* sync wait */
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gic_do_wait_for_rwp(rbase);
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@@ -404,9 +468,12 @@ void gic_enable_gicv3(void)
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gic_write_bpr1(0);
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/* Set specific IPI to NMI */
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writeb_relaxed(GICD_INT_NMI_PRI, rd_sgi_base + GIC_DIST_PRI + INTRID_CPU_STOP);
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writeb_relaxed(GICD_INT_NMI_PRI, rd_sgi_base + GIC_DIST_PRI + INTRID_MEMDUMP);
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writeb_relaxed(GICD_INT_NMI_PRI, rd_sgi_base + GIC_DIST_PRI + INTRID_STACK_TRACE);
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writeb_relaxed(GICD_INT_NMI_PRI,
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rd_sgi_base + GIC_DIST_PRI + INTRID_CPU_STOP);
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writeb_relaxed(GICD_INT_NMI_PRI,
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rd_sgi_base + GIC_DIST_PRI + INTRID_MULTI_NMI);
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writeb_relaxed(GICD_INT_NMI_PRI,
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rd_sgi_base + GIC_DIST_PRI + INTRID_STACK_TRACE);
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/* sync wait */
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gic_do_wait_for_rwp(rbase);
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