test perf_event: minor fixes(add signal handling. etc.)

Change-Id: I837d962bcaf13d3a523f80ff77f75b7fd51a98b7
2019-07-16 15:11:13 +09:00
parent 9c78d4d249
commit c52370b959
4 changed files with 445 additions and 0 deletions
--- a/test/perf_event/Makefile
+++ b/test/perf_event/Makefile
@@ -1,3 +1,13 @@
+CC?=gcc
+CPPFLAGS=-D_GNU_SOURCE
+CFLAGS=-Wall
+
 all: perf_test
+
+debug:CFLAGS+=-O0 -ggdb3
+debug:all
+
 perf_test: perf_test.o perftool.o
 perftool.o: perftool.c perftool.h
+clean:
+	rm -f perf_test.o perftool.o perf_test
--- a/test/perf_event/README
+++ b/test/perf_event/README
@@ -0,0 +1,72 @@
+==========
+How to run
+==========
+
+(1) Build McKernel
+(2) cd <mckernel>/test/perf_event
+(3) make
+(4) sh go_perf_test.sh
+
+============
+What to test
+============
+
+Check the performance monitoring of the following events.
+For each event, monitor the target space in user space,
+kernel space, or user+kernel space settings.
+
+[PERF_TYPE_HARDWARE]
+  1) PERF_COUNT_HW_CPU_CYCLES
+  2) PERF_COUNT_HW_INSTRUCTIONS
+  3) PERF_COUNT_HW_CACHE_REFERENCES
+  4) PERF_COUNT_HW_CACHE_MISSES
+  5) PERF_COUNT_HW_BRANCH_INSTRUCTIONS
+  6) PERF_COUNT_HW_BRANCH_MISSES
+  7) PERF_COUNT_HW_BUS_CYCLES
+  8) PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
+  9) PERF_COUNT_HW_STALLED_CYCLES_BACKEND
+ 10) PERF_COUNT_HW_REF_CPU_CYCLES
+
+[PERF_TYPE_HW_CACHE]
+  1) PERF_COUNT_HW_CACHE_L1D  | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+  2) PERF_COUNT_HW_CACHE_L1D  | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+  3) PERF_COUNT_HW_CACHE_L1D  | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+  4) PERF_COUNT_HW_CACHE_L1D  | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+  5) PERF_COUNT_HW_CACHE_L1D  | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+  6) PERF_COUNT_HW_CACHE_L1D  | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
+  7) PERF_COUNT_HW_CACHE_L1I  | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+  8) PERF_COUNT_HW_CACHE_L1I  | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+  9) PERF_COUNT_HW_CACHE_L1I  | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 10) PERF_COUNT_HW_CACHE_L1I  | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 11) PERF_COUNT_HW_CACHE_L1I  | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 12) PERF_COUNT_HW_CACHE_L1I  | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 13) PERF_COUNT_HW_CACHE_LL   | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 14) PERF_COUNT_HW_CACHE_LL   | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 15) PERF_COUNT_HW_CACHE_LL   | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 16) PERF_COUNT_HW_CACHE_LL   | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 17) PERF_COUNT_HW_CACHE_LL   | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 18) PERF_COUNT_HW_CACHE_LL   | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 19) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 20) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 21) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 22) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 23) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 24) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 25) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 26) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 27) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 28) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 29) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 30) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 31) PERF_COUNT_HW_CACHE_BPU  | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 32) PERF_COUNT_HW_CACHE_BPU  | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 33) PERF_COUNT_HW_CACHE_BPU  | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 34) PERF_COUNT_HW_CACHE_BPU  | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 35) PERF_COUNT_HW_CACHE_BPU  | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 36) PERF_COUNT_HW_CACHE_BPU  | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 37) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 38) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_READ     | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 39) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 40) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_WRITE    | PERF_COUNT_HW_CACHE_RESULT_MISS
+ 41) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ 42) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
--- a/test/perf_event/perftool.c
+++ b/test/perf_event/perftool.c
@@ -5,6 +5,8 @@
 #include <sys/ioctl.h>
 #include <linux/perf_event.h>
 #include <asm/unistd.h>
+#include <signal.h>
+#include <fcntl.h>

 //#include "perftool.h"

@@ -23,6 +25,12 @@ perf_event_open(struct perf_event_attr *hw_event, pid_t pid,
 	return ret;
 }

+void
+usr1_handler(int signum)
+{
+	puts("perf counter overflow.");
+}
+
 long
 pe_opener(long group_fd, int mode, int type, unsigned long config)
 {
@@ -53,7 +61,23 @@ pe_opener(long group_fd, int mode, int type, unsigned long config)
 	}

 	fd = perf_event_open(&pe, 0, -1, group_fd, 0);
+	if (fd != -1) {
+		struct sigaction act = {
+			.sa_handler = usr1_handler,
+		};

+		if (sigaction(SIGUSR1, &act, NULL)) {
+			close(fd);
+			fd = -1;
+		};
+	}
+
+	if (fd != -1) {
+		if (fcntl(fd, F_SETSIG, SIGUSR1)) {
+			close(fd);
+			fd = -1;
+		}
+	}
 	return fd;
 }

--- a/test/perf_event/result.log
+++ b/test/perf_event/result.log
@@ -0,0 +1,339 @@
+=========================
+aarch64
+=========================
+
+physical machine
+----------------
+# ./go_perf_test.sh
+mcstop+release.sh ... done
+mcreboot.sh -c 12,24,36,48 -m 2048M@4,2048M@5,2048M@6,2048M@7 -q 60 ... done
+[PERF_TYPE_HARDWARE all space]
+CPU_CYCLES             : 598879183
+INSTRUCTIONS           : 319639936
+CACHE_REFERENCES       : 291701521
+CACHE_MISSES           : 1996672
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : 4969
+BUS_CYCLES             : -1
+STALLED_CYCLES_FRONTEND: 459510
+STALLED_CYCLES_BACKEND : 447838339
+REF_CPU_CYCLES         : -1
+[HW_CACHE no exclude]
+L1D _OP_READ    _ACCESS: 291757634
+L1D _OP_READ    _MISS  : 1996674
+L1D _OP_WRITE   _ACCESS: 291675494
+L1D _OP_WRITE   _MISS  : 1996674
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: 109900150
+L1I _OP_READ    _MISS  : 239
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: -1
+DTLB_OP_READ    _MISS  : 893625
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: -1
+ITLB_OP_READ    _MISS  : 17
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: 42163456
+BPU _OP_READ    _MISS  : 5007
+BPU _OP_WRITE   _ACCESS: 42163456
+BPU _OP_WRITE   _MISS  : 4967
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+[HARDWARE exclude user space]
+CPU_CYCLES             : 597147551
+INSTRUCTIONS           : 573314
+CACHE_REFERENCES       : 31995
+CACHE_MISSES           : 214
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : 228
+BUS_CYCLES             : -1
+STALLED_CYCLES_FRONTEND: 20866
+STALLED_CYCLES_BACKEND : 1215677
+REF_CPU_CYCLES         : -1
+[HW_CACHE exclude user space]
+L1D _OP_READ    _ACCESS: 31883
+L1D _OP_READ    _MISS  : 216
+L1D _OP_WRITE   _ACCESS: 31998
+L1D _OP_WRITE   _MISS  : 217
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: 34195
+L1I _OP_READ    _MISS  : 148
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: -1
+DTLB_OP_READ    _MISS  : 39
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: -1
+ITLB_OP_READ    _MISS  : 7
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: 141350
+BPU _OP_READ    _MISS  : 203
+BPU _OP_WRITE   _ACCESS: 141350
+BPU _OP_WRITE   _MISS  : 217
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+[HARDWARE exclude kernel space]
+CPU_CYCLES             : 597505046
+INSTRUCTIONS           : 319066622
+CACHE_REFERENCES       : 291626611
+CACHE_MISSES           : 1996458
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : 4743
+BUS_CYCLES             : -1
+STALLED_CYCLES_FRONTEND: 437710
+STALLED_CYCLES_BACKEND : 446177603
+REF_CPU_CYCLES         : -1
+[HW_CACHE exclude kernel space]
+L1D _OP_READ    _ACCESS: 291624405
+L1D _OP_READ    _MISS  : 1996457
+L1D _OP_WRITE   _ACCESS: 291628743
+L1D _OP_WRITE   _MISS  : 1996459
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: 109868221
+L1I _OP_READ    _MISS  : 87
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: -1
+DTLB_OP_READ    _MISS  : 893411
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: -1
+ITLB_OP_READ    _MISS  : 9
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: 42022106
+BPU _OP_READ    _MISS  : 4729
+BPU _OP_WRITE   _ACCESS: 42022106
+BPU _OP_WRITE   _MISS  : 4733
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+
+virtual machine
+----------------
+# ./go_perf_test.sh
+mcstop+release.sh ... done
+mcreboot.sh -c 4-15 -m 16G ... done
+[PERF_TYPE_HARDWARE all space]
+CPU_CYCLES             : 2512315570
+INSTRUCTIONS           : -1
+CACHE_REFERENCES       : -1
+CACHE_MISSES           : -1
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : -1
+BUS_CYCLES             : -1
+STALLED_CYCLES_FRONTEND: -1
+STALLED_CYCLES_BACKEND : -1
+REF_CPU_CYCLES         : -1
+[HW_CACHE no exclude]
+L1D _OP_READ    _ACCESS: -1
+L1D _OP_READ    _MISS  : -1
+L1D _OP_WRITE   _ACCESS: -1
+L1D _OP_WRITE   _MISS  : -1
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: -1
+L1I _OP_READ    _MISS  : -1
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: -1
+DTLB_OP_READ    _MISS  : -1
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: -1
+ITLB_OP_READ    _MISS  : -1
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: -1
+BPU _OP_READ    _MISS  : -1
+BPU _OP_WRITE   _ACCESS: -1
+BPU _OP_WRITE   _MISS  : -1
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+[HARDWARE exclude user space]
+CPU_CYCLES             : 1631207786
+INSTRUCTIONS           : -1
+CACHE_REFERENCES       : -1
+CACHE_MISSES           : -1
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : -1
+BUS_CYCLES             : -1
+STALLED_CYCLES_FRONTEND: -1
+STALLED_CYCLES_BACKEND : -1
+REF_CPU_CYCLES         : -1
+[HW_CACHE exclude user space]
+L1D _OP_READ    _ACCESS: -1
+L1D _OP_READ    _MISS  : -1
+L1D _OP_WRITE   _ACCESS: -1
+L1D _OP_WRITE   _MISS  : -1
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: -1
+L1I _OP_READ    _MISS  : -1
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: -1
+DTLB_OP_READ    _MISS  : -1
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: -1
+ITLB_OP_READ    _MISS  : -1
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: -1
+BPU _OP_READ    _MISS  : -1
+BPU _OP_WRITE   _ACCESS: -1
+BPU _OP_WRITE   _MISS  : -1
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+[HARDWARE exclude kernel space]
+CPU_CYCLES             : 1595055278
+INSTRUCTIONS           : -1
+CACHE_REFERENCES       : -1
+CACHE_MISSES           : -1
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : -1
+BUS_CYCLES             : -1
+STALLED_CYCLES_FRONTEND: -1
+STALLED_CYCLES_BACKEND : -1
+REF_CPU_CYCLES         : -1
+[HW_CACHE exclude kernel space]
+L1D _OP_READ    _ACCESS: -1
+L1D _OP_READ    _MISS  : -1
+L1D _OP_WRITE   _ACCESS: -1
+L1D _OP_WRITE   _MISS  : -1
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: -1
+L1I _OP_READ    _MISS  : -1
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: -1
+DTLB_OP_READ    _MISS  : -1
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: -1
+ITLB_OP_READ    _MISS  : -1
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: -1
+BPU _OP_READ    _MISS  : -1
+BPU _OP_WRITE   _ACCESS: -1
+BPU _OP_WRITE   _MISS  : -1
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1