test perf_event: minor fixes(add signal handling. etc.)
Change-Id: I837d962bcaf13d3a523f80ff77f75b7fd51a98b7
This commit is contained in:
TOIDA,Suguru
@@ -1,3 +1,13 @@
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CC?=gcc
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CPPFLAGS=-D_GNU_SOURCE
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CFLAGS=-Wall
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all: perf_test
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all: perf_test
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debug:CFLAGS+=-O0 -ggdb3
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debug:all
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perf_test: perf_test.o perftool.o
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perf_test: perf_test.o perftool.o
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perftool.o: perftool.c perftool.h
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perftool.o: perftool.c perftool.h
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clean:
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rm -f perf_test.o perftool.o perf_test
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72
test/perf_event/README
Normal file
72
test/perf_event/README
Normal file
@@ -0,0 +1,72 @@
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==========
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How to run
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==========
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(1) Build McKernel
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(2) cd <mckernel>/test/perf_event
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(3) make
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(4) sh go_perf_test.sh
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============
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What to test
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============
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Check the performance monitoring of the following events.
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For each event, monitor the target space in user space,
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kernel space, or user+kernel space settings.
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[PERF_TYPE_HARDWARE]
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1) PERF_COUNT_HW_CPU_CYCLES
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2) PERF_COUNT_HW_INSTRUCTIONS
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3) PERF_COUNT_HW_CACHE_REFERENCES
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4) PERF_COUNT_HW_CACHE_MISSES
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5) PERF_COUNT_HW_BRANCH_INSTRUCTIONS
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6) PERF_COUNT_HW_BRANCH_MISSES
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7) PERF_COUNT_HW_BUS_CYCLES
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8) PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
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9) PERF_COUNT_HW_STALLED_CYCLES_BACKEND
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10) PERF_COUNT_HW_REF_CPU_CYCLES
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[PERF_TYPE_HW_CACHE]
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1) PERF_COUNT_HW_CACHE_L1D | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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2) PERF_COUNT_HW_CACHE_L1D | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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3) PERF_COUNT_HW_CACHE_L1D | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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4) PERF_COUNT_HW_CACHE_L1D | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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5) PERF_COUNT_HW_CACHE_L1D | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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6) PERF_COUNT_HW_CACHE_L1D | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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7) PERF_COUNT_HW_CACHE_L1I | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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8) PERF_COUNT_HW_CACHE_L1I | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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9) PERF_COUNT_HW_CACHE_L1I | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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10) PERF_COUNT_HW_CACHE_L1I | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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11) PERF_COUNT_HW_CACHE_L1I | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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12) PERF_COUNT_HW_CACHE_L1I | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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13) PERF_COUNT_HW_CACHE_LL | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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14) PERF_COUNT_HW_CACHE_LL | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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15) PERF_COUNT_HW_CACHE_LL | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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16) PERF_COUNT_HW_CACHE_LL | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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17) PERF_COUNT_HW_CACHE_LL | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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18) PERF_COUNT_HW_CACHE_LL | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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19) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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20) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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21) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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22) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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23) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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24) PERF_COUNT_HW_CACHE_DTLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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25) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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26) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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27) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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28) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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29) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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30) PERF_COUNT_HW_CACHE_ITLB | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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31) PERF_COUNT_HW_CACHE_BPU | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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32) PERF_COUNT_HW_CACHE_BPU | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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33) PERF_COUNT_HW_CACHE_BPU | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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34) PERF_COUNT_HW_CACHE_BPU | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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35) PERF_COUNT_HW_CACHE_BPU | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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36) PERF_COUNT_HW_CACHE_BPU | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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37) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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38) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_RESULT_MISS
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39) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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40) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_WRITE | PERF_COUNT_HW_CACHE_RESULT_MISS
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41) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_ACCESS
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42) PERF_COUNT_HW_CACHE_NODE | PERF_COUNT_HW_CACHE_OP_PREFETCH | PERF_COUNT_HW_CACHE_RESULT_MISS
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@@ -5,6 +5,8 @@
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#include <sys/ioctl.h>
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#include <sys/ioctl.h>
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#include <linux/perf_event.h>
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#include <linux/perf_event.h>
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#include <asm/unistd.h>
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#include <asm/unistd.h>
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#include <signal.h>
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#include <fcntl.h>
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//#include "perftool.h"
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//#include "perftool.h"
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@@ -23,6 +25,12 @@ perf_event_open(struct perf_event_attr *hw_event, pid_t pid,
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return ret;
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return ret;
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}
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}
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void
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usr1_handler(int signum)
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{
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puts("perf counter overflow.");
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}
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long
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long
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pe_opener(long group_fd, int mode, int type, unsigned long config)
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pe_opener(long group_fd, int mode, int type, unsigned long config)
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{
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{
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@@ -53,7 +61,23 @@ pe_opener(long group_fd, int mode, int type, unsigned long config)
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}
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}
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fd = perf_event_open(&pe, 0, -1, group_fd, 0);
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fd = perf_event_open(&pe, 0, -1, group_fd, 0);
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if (fd != -1) {
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struct sigaction act = {
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.sa_handler = usr1_handler,
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};
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if (sigaction(SIGUSR1, &act, NULL)) {
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close(fd);
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fd = -1;
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};
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}
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if (fd != -1) {
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if (fcntl(fd, F_SETSIG, SIGUSR1)) {
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close(fd);
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fd = -1;
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}
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}
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return fd;
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return fd;
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}
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}
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339
test/perf_event/result.log
Normal file
339
test/perf_event/result.log
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@@ -0,0 +1,339 @@
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=========================
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aarch64
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=========================
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physical machine
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----------------
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# ./go_perf_test.sh
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mcstop+release.sh ... done
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mcreboot.sh -c 12,24,36,48 -m 2048M@4,2048M@5,2048M@6,2048M@7 -q 60 ... done
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[PERF_TYPE_HARDWARE all space]
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CPU_CYCLES : 598879183
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INSTRUCTIONS : 319639936
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CACHE_REFERENCES : 291701521
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CACHE_MISSES : 1996672
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BRANCH_INSTRUCTIONS : -1
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BRANCH_MISSES : 4969
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BUS_CYCLES : -1
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STALLED_CYCLES_FRONTEND: 459510
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STALLED_CYCLES_BACKEND : 447838339
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REF_CPU_CYCLES : -1
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[HW_CACHE no exclude]
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L1D _OP_READ _ACCESS: 291757634
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L1D _OP_READ _MISS : 1996674
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L1D _OP_WRITE _ACCESS: 291675494
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L1D _OP_WRITE _MISS : 1996674
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L1D _OP_PREFETCH_ACCESS: -1
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L1D _OP_PREFETCH_MISS : -1
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L1I _OP_READ _ACCESS: 109900150
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L1I _OP_READ _MISS : 239
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L1I _OP_WRITE _ACCESS: -1
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L1I _OP_WRITE _MISS : -1
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L1I _OP_PREFETCH_ACCESS: -1
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L1I _OP_PREFETCH_MISS : -1
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LL _OP_READ _ACCESS: -1
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LL _OP_READ _MISS : -1
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LL _OP_WRITE _ACCESS: -1
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LL _OP_WRITE _MISS : -1
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LL _OP_PREFETCH_ACCESS: -1
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LL _OP_PREFETCH_MISS : -1
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DTLB_OP_READ _ACCESS: -1
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DTLB_OP_READ _MISS : 893625
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DTLB_OP_WRITE _ACCESS: -1
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DTLB_OP_WRITE _MISS : -1
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DTLB_OP_PREFETCH_ACCESS: -1
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DTLB_OP_PREFETCH_MISS : -1
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ITLB_OP_READ _ACCESS: -1
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ITLB_OP_READ _MISS : 17
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ITLB_OP_WRITE _ACCESS: -1
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ITLB_OP_WRITE _MISS : -1
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ITLB_OP_PREFETCH_ACCESS: -1
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ITLB_OP_PREFETCH_MISS : -1
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BPU _OP_READ _ACCESS: 42163456
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BPU _OP_READ _MISS : 5007
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BPU _OP_WRITE _ACCESS: 42163456
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BPU _OP_WRITE _MISS : 4967
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BPU _OP_PREFETCH_ACCESS: -1
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BPU _OP_PREFETCH_MISS : -1
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NODE_OP_READ _ACCESS: -1
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NODE_OP_READ _MISS : -1
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NODE_OP_WRITE _ACCESS: -1
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NODE_OP_WRITE _MISS : -1
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NODE_OP_PREFETCH_ACCESS: -1
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NODE_OP_PREFETCH_MISS : -1
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[HARDWARE exclude user space]
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CPU_CYCLES : 597147551
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INSTRUCTIONS : 573314
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CACHE_REFERENCES : 31995
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CACHE_MISSES : 214
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BRANCH_INSTRUCTIONS : -1
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BRANCH_MISSES : 228
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BUS_CYCLES : -1
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STALLED_CYCLES_FRONTEND: 20866
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STALLED_CYCLES_BACKEND : 1215677
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REF_CPU_CYCLES : -1
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[HW_CACHE exclude user space]
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L1D _OP_READ _ACCESS: 31883
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L1D _OP_READ _MISS : 216
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L1D _OP_WRITE _ACCESS: 31998
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L1D _OP_WRITE _MISS : 217
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L1D _OP_PREFETCH_ACCESS: -1
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L1D _OP_PREFETCH_MISS : -1
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L1I _OP_READ _ACCESS: 34195
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L1I _OP_READ _MISS : 148
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L1I _OP_WRITE _ACCESS: -1
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L1I _OP_WRITE _MISS : -1
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L1I _OP_PREFETCH_ACCESS: -1
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L1I _OP_PREFETCH_MISS : -1
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LL _OP_READ _ACCESS: -1
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LL _OP_READ _MISS : -1
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LL _OP_WRITE _ACCESS: -1
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LL _OP_WRITE _MISS : -1
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LL _OP_PREFETCH_ACCESS: -1
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LL _OP_PREFETCH_MISS : -1
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|
DTLB_OP_READ _ACCESS: -1
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DTLB_OP_READ _MISS : 39
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DTLB_OP_WRITE _ACCESS: -1
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|
DTLB_OP_WRITE _MISS : -1
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DTLB_OP_PREFETCH_ACCESS: -1
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|
DTLB_OP_PREFETCH_MISS : -1
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|
ITLB_OP_READ _ACCESS: -1
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|
ITLB_OP_READ _MISS : 7
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|
ITLB_OP_WRITE _ACCESS: -1
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||||||
|
ITLB_OP_WRITE _MISS : -1
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|
ITLB_OP_PREFETCH_ACCESS: -1
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||||||
|
ITLB_OP_PREFETCH_MISS : -1
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||||||
|
BPU _OP_READ _ACCESS: 141350
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||||||
|
BPU _OP_READ _MISS : 203
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||||||
|
BPU _OP_WRITE _ACCESS: 141350
|
||||||
|
BPU _OP_WRITE _MISS : 217
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||||||
|
BPU _OP_PREFETCH_ACCESS: -1
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|
BPU _OP_PREFETCH_MISS : -1
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||||||
|
NODE_OP_READ _ACCESS: -1
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||||||
|
NODE_OP_READ _MISS : -1
|
||||||
|
NODE_OP_WRITE _ACCESS: -1
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||||||
|
NODE_OP_WRITE _MISS : -1
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||||||
|
NODE_OP_PREFETCH_ACCESS: -1
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||||||
|
NODE_OP_PREFETCH_MISS : -1
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||||||
|
[HARDWARE exclude kernel space]
|
||||||
|
CPU_CYCLES : 597505046
|
||||||
|
INSTRUCTIONS : 319066622
|
||||||
|
CACHE_REFERENCES : 291626611
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||||||
|
CACHE_MISSES : 1996458
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||||||
|
BRANCH_INSTRUCTIONS : -1
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||||||
|
BRANCH_MISSES : 4743
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||||||
|
BUS_CYCLES : -1
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|
STALLED_CYCLES_FRONTEND: 437710
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|
STALLED_CYCLES_BACKEND : 446177603
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||||||
|
REF_CPU_CYCLES : -1
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||||||
|
[HW_CACHE exclude kernel space]
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||||||
|
L1D _OP_READ _ACCESS: 291624405
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||||||
|
L1D _OP_READ _MISS : 1996457
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||||||
|
L1D _OP_WRITE _ACCESS: 291628743
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||||||
|
L1D _OP_WRITE _MISS : 1996459
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||||||
|
L1D _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1D _OP_PREFETCH_MISS : -1
|
||||||
|
L1I _OP_READ _ACCESS: 109868221
|
||||||
|
L1I _OP_READ _MISS : 87
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||||||
|
L1I _OP_WRITE _ACCESS: -1
|
||||||
|
L1I _OP_WRITE _MISS : -1
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||||||
|
L1I _OP_PREFETCH_ACCESS: -1
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||||||
|
L1I _OP_PREFETCH_MISS : -1
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||||||
|
LL _OP_READ _ACCESS: -1
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||||||
|
LL _OP_READ _MISS : -1
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||||||
|
LL _OP_WRITE _ACCESS: -1
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||||||
|
LL _OP_WRITE _MISS : -1
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||||||
|
LL _OP_PREFETCH_ACCESS: -1
|
||||||
|
LL _OP_PREFETCH_MISS : -1
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||||||
|
DTLB_OP_READ _ACCESS: -1
|
||||||
|
DTLB_OP_READ _MISS : 893411
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||||||
|
DTLB_OP_WRITE _ACCESS: -1
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||||||
|
DTLB_OP_WRITE _MISS : -1
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||||||
|
DTLB_OP_PREFETCH_ACCESS: -1
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||||||
|
DTLB_OP_PREFETCH_MISS : -1
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||||||
|
ITLB_OP_READ _ACCESS: -1
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||||||
|
ITLB_OP_READ _MISS : 9
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||||||
|
ITLB_OP_WRITE _ACCESS: -1
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||||||
|
ITLB_OP_WRITE _MISS : -1
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||||||
|
ITLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
ITLB_OP_PREFETCH_MISS : -1
|
||||||
|
BPU _OP_READ _ACCESS: 42022106
|
||||||
|
BPU _OP_READ _MISS : 4729
|
||||||
|
BPU _OP_WRITE _ACCESS: 42022106
|
||||||
|
BPU _OP_WRITE _MISS : 4733
|
||||||
|
BPU _OP_PREFETCH_ACCESS: -1
|
||||||
|
BPU _OP_PREFETCH_MISS : -1
|
||||||
|
NODE_OP_READ _ACCESS: -1
|
||||||
|
NODE_OP_READ _MISS : -1
|
||||||
|
NODE_OP_WRITE _ACCESS: -1
|
||||||
|
NODE_OP_WRITE _MISS : -1
|
||||||
|
NODE_OP_PREFETCH_ACCESS: -1
|
||||||
|
NODE_OP_PREFETCH_MISS : -1
|
||||||
|
|
||||||
|
virtual machine
|
||||||
|
----------------
|
||||||
|
# ./go_perf_test.sh
|
||||||
|
mcstop+release.sh ... done
|
||||||
|
mcreboot.sh -c 4-15 -m 16G ... done
|
||||||
|
[PERF_TYPE_HARDWARE all space]
|
||||||
|
CPU_CYCLES : 2512315570
|
||||||
|
INSTRUCTIONS : -1
|
||||||
|
CACHE_REFERENCES : -1
|
||||||
|
CACHE_MISSES : -1
|
||||||
|
BRANCH_INSTRUCTIONS : -1
|
||||||
|
BRANCH_MISSES : -1
|
||||||
|
BUS_CYCLES : -1
|
||||||
|
STALLED_CYCLES_FRONTEND: -1
|
||||||
|
STALLED_CYCLES_BACKEND : -1
|
||||||
|
REF_CPU_CYCLES : -1
|
||||||
|
[HW_CACHE no exclude]
|
||||||
|
L1D _OP_READ _ACCESS: -1
|
||||||
|
L1D _OP_READ _MISS : -1
|
||||||
|
L1D _OP_WRITE _ACCESS: -1
|
||||||
|
L1D _OP_WRITE _MISS : -1
|
||||||
|
L1D _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1D _OP_PREFETCH_MISS : -1
|
||||||
|
L1I _OP_READ _ACCESS: -1
|
||||||
|
L1I _OP_READ _MISS : -1
|
||||||
|
L1I _OP_WRITE _ACCESS: -1
|
||||||
|
L1I _OP_WRITE _MISS : -1
|
||||||
|
L1I _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1I _OP_PREFETCH_MISS : -1
|
||||||
|
LL _OP_READ _ACCESS: -1
|
||||||
|
LL _OP_READ _MISS : -1
|
||||||
|
LL _OP_WRITE _ACCESS: -1
|
||||||
|
LL _OP_WRITE _MISS : -1
|
||||||
|
LL _OP_PREFETCH_ACCESS: -1
|
||||||
|
LL _OP_PREFETCH_MISS : -1
|
||||||
|
DTLB_OP_READ _ACCESS: -1
|
||||||
|
DTLB_OP_READ _MISS : -1
|
||||||
|
DTLB_OP_WRITE _ACCESS: -1
|
||||||
|
DTLB_OP_WRITE _MISS : -1
|
||||||
|
DTLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
DTLB_OP_PREFETCH_MISS : -1
|
||||||
|
ITLB_OP_READ _ACCESS: -1
|
||||||
|
ITLB_OP_READ _MISS : -1
|
||||||
|
ITLB_OP_WRITE _ACCESS: -1
|
||||||
|
ITLB_OP_WRITE _MISS : -1
|
||||||
|
ITLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
ITLB_OP_PREFETCH_MISS : -1
|
||||||
|
BPU _OP_READ _ACCESS: -1
|
||||||
|
BPU _OP_READ _MISS : -1
|
||||||
|
BPU _OP_WRITE _ACCESS: -1
|
||||||
|
BPU _OP_WRITE _MISS : -1
|
||||||
|
BPU _OP_PREFETCH_ACCESS: -1
|
||||||
|
BPU _OP_PREFETCH_MISS : -1
|
||||||
|
NODE_OP_READ _ACCESS: -1
|
||||||
|
NODE_OP_READ _MISS : -1
|
||||||
|
NODE_OP_WRITE _ACCESS: -1
|
||||||
|
NODE_OP_WRITE _MISS : -1
|
||||||
|
NODE_OP_PREFETCH_ACCESS: -1
|
||||||
|
NODE_OP_PREFETCH_MISS : -1
|
||||||
|
[HARDWARE exclude user space]
|
||||||
|
CPU_CYCLES : 1631207786
|
||||||
|
INSTRUCTIONS : -1
|
||||||
|
CACHE_REFERENCES : -1
|
||||||
|
CACHE_MISSES : -1
|
||||||
|
BRANCH_INSTRUCTIONS : -1
|
||||||
|
BRANCH_MISSES : -1
|
||||||
|
BUS_CYCLES : -1
|
||||||
|
STALLED_CYCLES_FRONTEND: -1
|
||||||
|
STALLED_CYCLES_BACKEND : -1
|
||||||
|
REF_CPU_CYCLES : -1
|
||||||
|
[HW_CACHE exclude user space]
|
||||||
|
L1D _OP_READ _ACCESS: -1
|
||||||
|
L1D _OP_READ _MISS : -1
|
||||||
|
L1D _OP_WRITE _ACCESS: -1
|
||||||
|
L1D _OP_WRITE _MISS : -1
|
||||||
|
L1D _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1D _OP_PREFETCH_MISS : -1
|
||||||
|
L1I _OP_READ _ACCESS: -1
|
||||||
|
L1I _OP_READ _MISS : -1
|
||||||
|
L1I _OP_WRITE _ACCESS: -1
|
||||||
|
L1I _OP_WRITE _MISS : -1
|
||||||
|
L1I _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1I _OP_PREFETCH_MISS : -1
|
||||||
|
LL _OP_READ _ACCESS: -1
|
||||||
|
LL _OP_READ _MISS : -1
|
||||||
|
LL _OP_WRITE _ACCESS: -1
|
||||||
|
LL _OP_WRITE _MISS : -1
|
||||||
|
LL _OP_PREFETCH_ACCESS: -1
|
||||||
|
LL _OP_PREFETCH_MISS : -1
|
||||||
|
DTLB_OP_READ _ACCESS: -1
|
||||||
|
DTLB_OP_READ _MISS : -1
|
||||||
|
DTLB_OP_WRITE _ACCESS: -1
|
||||||
|
DTLB_OP_WRITE _MISS : -1
|
||||||
|
DTLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
DTLB_OP_PREFETCH_MISS : -1
|
||||||
|
ITLB_OP_READ _ACCESS: -1
|
||||||
|
ITLB_OP_READ _MISS : -1
|
||||||
|
ITLB_OP_WRITE _ACCESS: -1
|
||||||
|
ITLB_OP_WRITE _MISS : -1
|
||||||
|
ITLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
ITLB_OP_PREFETCH_MISS : -1
|
||||||
|
BPU _OP_READ _ACCESS: -1
|
||||||
|
BPU _OP_READ _MISS : -1
|
||||||
|
BPU _OP_WRITE _ACCESS: -1
|
||||||
|
BPU _OP_WRITE _MISS : -1
|
||||||
|
BPU _OP_PREFETCH_ACCESS: -1
|
||||||
|
BPU _OP_PREFETCH_MISS : -1
|
||||||
|
NODE_OP_READ _ACCESS: -1
|
||||||
|
NODE_OP_READ _MISS : -1
|
||||||
|
NODE_OP_WRITE _ACCESS: -1
|
||||||
|
NODE_OP_WRITE _MISS : -1
|
||||||
|
NODE_OP_PREFETCH_ACCESS: -1
|
||||||
|
NODE_OP_PREFETCH_MISS : -1
|
||||||
|
[HARDWARE exclude kernel space]
|
||||||
|
CPU_CYCLES : 1595055278
|
||||||
|
INSTRUCTIONS : -1
|
||||||
|
CACHE_REFERENCES : -1
|
||||||
|
CACHE_MISSES : -1
|
||||||
|
BRANCH_INSTRUCTIONS : -1
|
||||||
|
BRANCH_MISSES : -1
|
||||||
|
BUS_CYCLES : -1
|
||||||
|
STALLED_CYCLES_FRONTEND: -1
|
||||||
|
STALLED_CYCLES_BACKEND : -1
|
||||||
|
REF_CPU_CYCLES : -1
|
||||||
|
[HW_CACHE exclude kernel space]
|
||||||
|
L1D _OP_READ _ACCESS: -1
|
||||||
|
L1D _OP_READ _MISS : -1
|
||||||
|
L1D _OP_WRITE _ACCESS: -1
|
||||||
|
L1D _OP_WRITE _MISS : -1
|
||||||
|
L1D _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1D _OP_PREFETCH_MISS : -1
|
||||||
|
L1I _OP_READ _ACCESS: -1
|
||||||
|
L1I _OP_READ _MISS : -1
|
||||||
|
L1I _OP_WRITE _ACCESS: -1
|
||||||
|
L1I _OP_WRITE _MISS : -1
|
||||||
|
L1I _OP_PREFETCH_ACCESS: -1
|
||||||
|
L1I _OP_PREFETCH_MISS : -1
|
||||||
|
LL _OP_READ _ACCESS: -1
|
||||||
|
LL _OP_READ _MISS : -1
|
||||||
|
LL _OP_WRITE _ACCESS: -1
|
||||||
|
LL _OP_WRITE _MISS : -1
|
||||||
|
LL _OP_PREFETCH_ACCESS: -1
|
||||||
|
LL _OP_PREFETCH_MISS : -1
|
||||||
|
DTLB_OP_READ _ACCESS: -1
|
||||||
|
DTLB_OP_READ _MISS : -1
|
||||||
|
DTLB_OP_WRITE _ACCESS: -1
|
||||||
|
DTLB_OP_WRITE _MISS : -1
|
||||||
|
DTLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
DTLB_OP_PREFETCH_MISS : -1
|
||||||
|
ITLB_OP_READ _ACCESS: -1
|
||||||
|
ITLB_OP_READ _MISS : -1
|
||||||
|
ITLB_OP_WRITE _ACCESS: -1
|
||||||
|
ITLB_OP_WRITE _MISS : -1
|
||||||
|
ITLB_OP_PREFETCH_ACCESS: -1
|
||||||
|
ITLB_OP_PREFETCH_MISS : -1
|
||||||
|
BPU _OP_READ _ACCESS: -1
|
||||||
|
BPU _OP_READ _MISS : -1
|
||||||
|
BPU _OP_WRITE _ACCESS: -1
|
||||||
|
BPU _OP_WRITE _MISS : -1
|
||||||
|
BPU _OP_PREFETCH_ACCESS: -1
|
||||||
|
BPU _OP_PREFETCH_MISS : -1
|
||||||
|
NODE_OP_READ _ACCESS: -1
|
||||||
|
NODE_OP_READ _MISS : -1
|
||||||
|
NODE_OP_WRITE _ACCESS: -1
|
||||||
|
NODE_OP_WRITE _MISS : -1
|
||||||
|
NODE_OP_PREFETCH_ACCESS: -1
|
||||||
|
NODE_OP_PREFETCH_MISS : -1
|
||||||
Reference in New Issue
Block a user