add arm64 support
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
This commit is contained in:
Takayuki Okamoto
198
arch/arm64/kernel/include/ptrace.h
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198
arch/arm64/kernel/include/ptrace.h
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/* ptrace.h COPYRIGHT FUJITSU LIMITED 2015-2017 */
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#ifndef __HEADER_ARM64_COMMON_PTRACE_H
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#define __HEADER_ARM64_COMMON_PTRACE_H
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/*
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* PSR bits
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*/
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#define PSR_MODE_EL0t 0x00000000
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#define PSR_MODE_EL1t 0x00000004
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#define PSR_MODE_EL1h 0x00000005
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#define PSR_MODE_EL2t 0x00000008
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#define PSR_MODE_EL2h 0x00000009
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#define PSR_MODE_EL3t 0x0000000c
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#define PSR_MODE_EL3h 0x0000000d
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#define PSR_MODE_MASK 0x0000000f
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/* AArch32 CPSR bits */
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#define PSR_MODE32_BIT 0x00000010
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/* AArch64 SPSR bits */
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#define PSR_F_BIT 0x00000040
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#define PSR_I_BIT 0x00000080
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#define PSR_A_BIT 0x00000100
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#define PSR_D_BIT 0x00000200
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#define PSR_Q_BIT 0x08000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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#define PSR_N_BIT 0x80000000
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/*
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* Groups of PSR bits
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*/
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#define PSR_f 0xff000000 /* Flags */
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#define PSR_s 0x00ff0000 /* Status */
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#define PSR_x 0x0000ff00 /* Extension */
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#define PSR_c 0x000000ff /* Control */
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/* Current Exception Level values, as contained in CurrentEL */
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#define CurrentEL_EL1 (1 << 2)
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#define CurrentEL_EL2 (2 << 2)
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/* thread->ptrace_debugreg lower-area and higher-area */
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#define HWS_BREAK 0
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#define HWS_WATCH 1
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#ifndef __ASSEMBLY__
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#include <ihk/types.h>
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struct user_hwdebug_state {
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uint32_t dbg_info;
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uint32_t pad;
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struct {
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uint64_t addr;
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uint32_t ctrl;
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uint32_t pad;
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} dbg_regs[16];
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};
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struct user_fpsimd_state {
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__uint128_t vregs[32];
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uint32_t fpsr;
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uint32_t fpcr;
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uint32_t __reserved[2];
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};
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extern unsigned int ptrace_hbp_get_resource_info(unsigned int note_type);
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/* SVE/FP/SIMD state (NT_ARM_SVE) */
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struct user_sve_header {
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uint32_t size; /* total meaningful regset content in bytes */
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uint32_t max_size; /* maxmium possible size for this thread */
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uint16_t vl; /* current vector length */
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uint16_t max_vl; /* maximum possible vector length */
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uint16_t flags;
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uint16_t __reserved;
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};
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/* Definitions for user_sve_header.flags: */
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#define SVE_PT_REGS_MASK (1 << 0)
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#define SVE_PT_REGS_FPSIMD 0
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#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
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#define SVE_PT_VL_THREAD PR_SVE_SET_VL_THREAD
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#define SVE_PT_VL_INHERIT PR_SVE_SET_VL_INHERIT
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#define SVE_PT_VL_ONEXEC PR_SVE_SET_VL_ONEXEC
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/*
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* The remainder of the SVE state follows struct user_sve_header. The
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* total size of the SVE state (including header) depends on the
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* metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size
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* of the state in bytes, including the header.
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*
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* Refer to <asm/sigcontext.h> for details of how to pass the correct
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* "vq" argument to these macros.
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*/
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/* Offset from the start of struct user_sve_header to the register data */
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#define SVE_PT_REGS_OFFSET ((sizeof(struct sve_context) + 15) / 16 * 16)
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/*
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* The register data content and layout depends on the value of the
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* flags field.
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*/
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/*
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* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
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*
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* The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
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* struct user_fpsimd_state. Additional data might be appended in the
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* future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
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* SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
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* sizeof(struct user_fpsimd_state).
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*/
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#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
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#define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state))
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/*
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* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
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*
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* The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
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* SVE_PT_SVE_SIZE(vq, flags).
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*
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* Additional macros describe the contents and layout of the payload.
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* For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
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* the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
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* the size in bytes:
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*
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* x type description
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* - ---- -----------
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* ZREGS \
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* ZREG |
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* PREGS | refer to <asm/sigcontext.h>
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* PREG |
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* FFR /
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*
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* FPSR uint32_t FPSR
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* FPCR uint32_t FPCR
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*
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* Additional data might be appended in the future.
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*/
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#define SVE_PT_SVE_ZREG_SIZE(vq) SVE_SIG_ZREG_SIZE(vq)
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#define SVE_PT_SVE_PREG_SIZE(vq) SVE_SIG_PREG_SIZE(vq)
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#define SVE_PT_SVE_FFR_SIZE(vq) SVE_SIG_FFR_SIZE(vq)
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#define SVE_PT_SVE_FPSR_SIZE sizeof(uint32_t)
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#define SVE_PT_SVE_FPCR_SIZE sizeof(uint32_t)
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#define __SVE_SIG_TO_PT(offset) \
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((offset) - SVE_SIG_REGS_OFFSET + SVE_PT_REGS_OFFSET)
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#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
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#define SVE_PT_SVE_ZREGS_OFFSET \
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__SVE_SIG_TO_PT(SVE_SIG_ZREGS_OFFSET)
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#define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
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__SVE_SIG_TO_PT(SVE_SIG_ZREG_OFFSET(vq, n))
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#define SVE_PT_SVE_ZREGS_SIZE(vq) \
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(SVE_PT_SVE_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
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#define SVE_PT_SVE_PREGS_OFFSET(vq) \
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__SVE_SIG_TO_PT(SVE_SIG_PREGS_OFFSET(vq))
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#define SVE_PT_SVE_PREG_OFFSET(vq, n) \
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__SVE_SIG_TO_PT(SVE_SIG_PREG_OFFSET(vq, n))
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#define SVE_PT_SVE_PREGS_SIZE(vq) \
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(SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - \
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SVE_PT_SVE_PREGS_OFFSET(vq))
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#define SVE_PT_SVE_FFR_OFFSET(vq) \
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__SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq))
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#define SVE_PT_SVE_FPSR_OFFSET(vq) \
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((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + 15) / 16 * 16)
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#define SVE_PT_SVE_FPCR_OFFSET(vq) \
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(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
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/*
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* Any future extension appended after FPCR must be aligned to the next
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* 128-bit boundary.
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*/
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#define SVE_PT_SVE_SIZE(vq, flags) \
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((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE - \
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SVE_PT_SVE_OFFSET + 15) / 16 * 16)
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#define SVE_PT_SIZE(vq, flags) \
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(((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \
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SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
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: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
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#endif /* !__ASSEMBLY__ */
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#endif /* !__HEADER_ARM64_COMMON_PTRACE_H */
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