add arm64 support
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
This commit is contained in:
Takayuki Okamoto
191
arch/arm64/kernel/context.c
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191
arch/arm64/kernel/context.c
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/* context.c COPYRIGHT FUJITSU LIMITED 2015-2017 */
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#include <ihk/context.h>
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#include <ihk/debug.h>
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#include <thread_info.h>
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#include <cputype.h>
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#include <mmu_context.h>
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#include <arch-memory.h>
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#include <irqflags.h>
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#include <lwk/compiler.h>
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#include <bitops.h>
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/* @ref.impl arch/arm64/include/asm/mmu_context.h::MAX_ASID_BITS */
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#define MAX_ASID_BITS 16
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#define ASID_FIRST_VERSION (1 << MAX_ASID_BITS)
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#define ASID_MASK ((1 << MAX_ASID_BITS) - 1)
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#define VERSION_MASK (0xFFFF << MAX_ASID_BITS)
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/* @ref.impl arch/arm64/mm/context.c::asid_bits */
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#define asid_bits(reg) \
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(((read_cpuid(ID_AA64MMFR0_EL1) & 0xf0) >> 2) + 8)
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#define MAX_CTX_NR (1UL << MAX_ASID_BITS)
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DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR) = { 1 }; /* context number 0 reserved. */
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/* cpu_asid lock */
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static ihk_spinlock_t cpu_asid_lock = SPIN_LOCK_UNLOCKED;
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/* last allocation ASID, initialized by 0x0001_0000 */
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static unsigned int cpu_last_asid = ASID_FIRST_VERSION;
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/* @ref.impl arch/arm64/mm/context.c::set_mm_context */
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/* set asid for kernel_context_t.context */
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static void set_mm_context(struct page_table *pgtbl, unsigned int asid)
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{
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unsigned int context = get_address_space_id(pgtbl);
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if (likely((context ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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set_address_space_id(pgtbl, asid);
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}
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}
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/* @ref.impl arch/arm64/mm/context.c::__new_context */
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/* ASID allocation for new process function */
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static inline void __new_context(struct page_table *pgtbl)
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{
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unsigned int asid;
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unsigned int bits = asid_bits();
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unsigned long flags;
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unsigned int context = get_address_space_id(pgtbl);
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unsigned long index = 0;
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flags = ihk_mc_spinlock_lock(&cpu_asid_lock);
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/* already assigned context number? */
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if (!unlikely((context ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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/* true, unnecessary assigned context number */
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ihk_mc_spinlock_unlock(&cpu_asid_lock, flags);
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return;
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}
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/* false, necessary assigned context number */
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/* search from the previous assigned number */
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index = (cpu_last_asid & ASID_MASK) + 1;
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asid = find_next_zero_bit(mmu_context_bmap, MAX_CTX_NR, index);
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/* upper limit exceeded */
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if (asid >= (1 << bits)) {
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/* re assigned context number, search from 1 */
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asid = find_next_zero_bit(mmu_context_bmap, index, 1);
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/* upper previous assigned number, goto panic */
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if (unlikely(asid >= index)) {
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ihk_mc_spinlock_unlock(&cpu_asid_lock, flags);
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panic("__new_context(): PANIC: Context Number Depletion.\n");
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}
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}
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/* set assigned context number bitmap */
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mmu_context_bmap[asid >> 6] |= (1UL << (asid & 63));
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/* set previous assigned context number */
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cpu_last_asid = asid | (cpu_last_asid & VERSION_MASK);
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set_mm_context(pgtbl, cpu_last_asid);
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ihk_mc_spinlock_unlock(&cpu_asid_lock, flags);
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}
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void free_mmu_context(struct page_table *pgtbl)
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{
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unsigned int context = get_address_space_id(pgtbl);
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unsigned int nr = context & ASID_MASK;
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unsigned long flags = ihk_mc_spinlock_lock(&cpu_asid_lock);
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/* clear used context number bitmap */
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mmu_context_bmap[nr >> 6] &= ~(1UL << (nr & 63));
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ihk_mc_spinlock_unlock(&cpu_asid_lock, flags);
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}
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/* set ttbr0 assembler code extern */
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/* in arch/arm64/kernel/proc.S */
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extern void *cpu_do_switch_mm(translation_table_t* tt_pa, unsigned int asid);
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/* @ref.impl arch/arm64/include/asm/mmu_context.h::switch_new_context */
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/* ASID allocation for new process */
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static inline void switch_new_context(struct page_table *pgtbl)
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{
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unsigned long flags;
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translation_table_t* tt_pa;
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unsigned int context;
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/* ASID allocation */
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__new_context(pgtbl);
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context = get_address_space_id(pgtbl);
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/* disable interrupt save */
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flags = cpu_disable_interrupt_save();
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tt_pa = get_translation_table_as_paddr(pgtbl);
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cpu_do_switch_mm(tt_pa, context & ASID_MASK);
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/* interrupt restore */
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cpu_restore_interrupt(flags);
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}
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/* @ref.impl arch/arm64/include/asm/mmu_context.h::check_and_switch_context */
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/* ASID allocation */
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void switch_mm(struct page_table *pgtbl)
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{
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unsigned int context = get_address_space_id(pgtbl);
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/* During switch_mm, you want to disable the TTBR */
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cpu_set_reserved_ttbr0();
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/* check new process or existing process */
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if (!((context ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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translation_table_t* tt_pa;
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/* for existing process */
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tt_pa = get_translation_table_as_paddr(pgtbl);
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cpu_do_switch_mm(tt_pa, context & ASID_MASK);
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/* TODO: tif_switch_mm / after context switch */
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// } else if (irqs_disabled()) {
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// /*
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// * Defer the new ASID allocation until after the context
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// * switch critical region since __new_context() cannot be
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// * called with interrupts disabled.
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// */
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// set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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} else {
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/* for new process */
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/* ASID allocation & set ttbr0 */
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switch_new_context(pgtbl);
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}
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}
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/* context switch assembler code extern */
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/* in arch/arm64/kernel/entry.S */
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extern void *cpu_switch_to(struct thread_info *prev, struct thread_info *next, void *prev_proc);
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/* context switch C function */
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/* TODO: fpreg etc.. save & restore */
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static inline void *switch_to(struct thread_info *prev,
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struct thread_info *next,
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void *prev_proc)
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{
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void *last = NULL;
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next->cpu = ihk_mc_get_processor_id();
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last = cpu_switch_to(prev, next, prev_proc);
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return last;
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}
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/* common unit I/F, for context switch */
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void *ihk_mc_switch_context(ihk_mc_kernel_context_t *old_ctx,
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ihk_mc_kernel_context_t *new_ctx,
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void *prev)
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{
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struct thread_info *prev_ti = NULL;
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struct thread_info *next_ti = NULL;
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/* get next thread_info addr */
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next_ti = new_ctx->thread;
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if (likely(old_ctx)) {
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/* get prev thread_info addr */
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prev_ti = old_ctx->thread;
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}
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/* switch next thread_info & process */
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return switch_to(prev_ti, next_ti, prev);
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}
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