Tofu: initial version
Change-Id: I9c464d5af883c18715a97ca9e9981cf73b260f90
This commit is contained in:
committed by
Masamichi Takagi
parent
fe83deb3db
commit
92902d36fc
@@ -80,6 +80,10 @@ static inline uint64_t __raw_readq(const volatile void *addr)
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return val;
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}
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/* IO barriers */
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#define __iormb() rmb()
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#define __iowmb() wmb()
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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@@ -95,5 +99,20 @@ static inline uint64_t __raw_readq(const volatile void *addr)
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#define writel_relaxed(v,c) ((void)__raw_writel((uint32_t)(v),(c)))
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#define writeq_relaxed(v,c) ((void)__raw_writeq((uint64_t)(v),(c)))
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access.
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*/
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#define readb(c) ({ uint8_t __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ uint16_t __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ uint32_t __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ uint64_t __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
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#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
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#endif /* __KERNEL__ */
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#endif /* __ASM_IO_H */
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