From 6ed2e5ffc1e0a5258228791bcc90b08e55d18072 Mon Sep 17 00:00:00 2001 From: Balazs Gerofi Date: Mon, 28 Jan 2019 11:06:30 +0900 Subject: [PATCH] Fix ThunderX2 write-combined PTE flag insanity Change-Id: I59999a680b556acf3e22ac516f4758e3aee7f355 --- arch/arm64/kernel/include/cputype.h | 63 ++++++++++++++++++- arch/arm64/kernel/memory.c | 15 ++++- executer/kernel/mcctrl/arch/arm64/archdeps.c | 9 --- .../mcctrl/arch/arm64/include/archdeps.h | 17 ++++- 4 files changed, 92 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/include/cputype.h b/arch/arm64/kernel/include/cputype.h index 8feed533..bb2243bb 100644 --- a/arch/arm64/kernel/include/cputype.h +++ b/arch/arm64/kernel/include/cputype.h @@ -25,6 +25,11 @@ #define MIDR_PARTNUM(midr) \ (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_ARCHITECTURE(midr) \ + (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) + #define MIDR_VARIANT_SHIFT 20 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) #define MIDR_VARIANT(midr) \ @@ -35,7 +40,63 @@ #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) -#define ARM_CPU_IMP_CAVIUM 0x43 +#define MIDR_CPU_MODEL(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define MIDR_CPU_VAR_REV(var, rev) \ + (((var) << MIDR_VARIANT_SHIFT) | (rev)) + +#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ + MIDR_ARCHITECTURE_MASK) + +#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ +({ \ + u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ + u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ + _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ +}) + +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_APM 0x50 +#define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_BRCM 0x42 +#define ARM_CPU_IMP_QCOM 0x51 + +#define ARM_CPU_PART_AEM_V8 0xD0F +#define ARM_CPU_PART_FOUNDATION 0xD00 +#define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 +#define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A + +#define APM_CPU_PART_POTENZA 0x000 + +#define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 +#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF + +#define BRCM_CPU_PART_VULCAN 0x516 + +#define QCOM_CPU_PART_FALKOR_V1 0x800 +#define QCOM_CPU_PART_FALKOR 0xC00 + +#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) +#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) +#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/memory.c b/arch/arm64/kernel/memory.c index a7aa9ff9..5d84dab3 100644 --- a/arch/arm64/kernel/memory.c +++ b/arch/arm64/kernel/memory.c @@ -16,6 +16,7 @@ #include #include #include +#include //#define DEBUG @@ -1020,7 +1021,19 @@ static unsigned long attr_to_pageattr(enum ihk_mc_pt_attribute attr) if (attr & PTATTR_UNCACHABLE) { pte |= PROT_DEFAULT | PTE_ATTRINDX(MT_DEVICE_nGnRE); } else if (attr & PTATTR_WRITE_COMBINED) { - pte |= PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC); + switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { + /* + * Fix up arm64 braindamage of using NORMAL_NC for write + * combining when Device GRE exists specifically for the + * purpose. Needed on ThunderX2. + */ + case MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN): + case MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2): + pte |= PROT_DEFAULT | PTE_ATTRINDX(MT_DEVICE_GRE); + break; + default: + pte |= PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC); + } } else { pte |= PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL); } diff --git a/executer/kernel/mcctrl/arch/arm64/archdeps.c b/executer/kernel/mcctrl/arch/arm64/archdeps.c index e7871ea6..e4199dbe 100644 --- a/executer/kernel/mcctrl/arch/arm64/archdeps.c +++ b/executer/kernel/mcctrl/arch/arm64/archdeps.c @@ -304,12 +304,3 @@ out: error, rva, rpa, pgsize); return error; } - -#ifdef POSTK_DEBUG_ARCH_DEP_12 -#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC) -static inline bool pte_is_write_combined(pte_t pte) -{ - return ((pte_val(pte) & PTE_ATTRINDX_MASK) == PFN_WRITE_COMBINED); -} -#endif /* POSTK_DEBUG_ARCH_DEP_12 */ - diff --git a/executer/kernel/mcctrl/arch/arm64/include/archdeps.h b/executer/kernel/mcctrl/arch/arm64/include/archdeps.h index 0ef7fff2..cf2163db 100644 --- a/executer/kernel/mcctrl/arch/arm64/include/archdeps.h +++ b/executer/kernel/mcctrl/arch/arm64/include/archdeps.h @@ -10,10 +10,25 @@ extern int translate_rva_to_rpa(ihk_os_t os, unsigned long rpt, unsigned long rv unsigned long *rpap, unsigned long *pgsizep); #ifdef POSTK_DEBUG_ARCH_DEP_12 -#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC) +#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC) static inline bool pte_is_write_combined(pte_t pte) { +#if defined(MIDR_CPU_MODEL_MASK) + /* + * Fix up arm64 braindamage of using NORMAL_NC for write + * combining when Device GRE exists specifically for the + * purpose. Needed on ThunderX2. + */ + switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { +#if defined(ARM_CPU_IMP_BRCM) && defined(BRCM_CPU_PART_VULCAN) + case MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN): +#endif + case MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2): + return ((pte_val(pte) & PTE_ATTRINDX_MASK) == + PTE_ATTRINDX(MT_DEVICE_GRE)); + } +#endif return ((pte_val(pte) & PTE_ATTRINDX_MASK) == PFN_WRITE_COMBINED); } #endif /* POSTK_DEBUG_ARCH_DEP_12 */