perf: update event structure

Change-Id: I5bc0fdd42db509b5d2daca7d97e29ad1f7d11f1a

arch/arm64/kernel/include/ihk/atomic.h

@@ -147,6 +147,8 @@ static inline void ihk_atomic64_add(long i, ihk_atomic64_t *v)
 /* @ref.impl arch/arm64/include/asm/atomic.h::atomic64_inc */
 #define ihk_atomic64_inc(v)			ihk_atomic64_add(1LL, (v))
 
+#define ihk_atomic64_cmpxchg(p, o, n) cmpxchg(&((p)->counter64), o, n)
+
 /***********************************************************************
  * others
  */

arch/arm64/kernel/perfctr.c

@@ -272,3 +272,26 @@ int ihk_mc_event_set_period(struct mc_perf_event *event)
 
 	return ret;
 }
+
+uint64_t ihk_mc_event_update(struct mc_perf_event *event)
+{
+	struct hw_perf_event *hwc = &event->hw;
+	int64_t delta;
+	uint64_t prev_raw_count, new_raw_count;
+	uint64_t max_period = arm_pmu_event_max_period(event);
+
+again:
+	prev_raw_count = ihk_atomic64_read(&hwc->prev_count);
+	new_raw_count = cpu_pmu.read_counter(event->counter_id);
+
+	if (ihk_atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+			     new_raw_count) != prev_raw_count)
+		goto again;
+
+	delta = (new_raw_count - prev_raw_count) & max_period;
+
+	ihk_atomic64_add(delta, &event->count);
+	ihk_atomic64_add(-delta, &hwc->period_left);
+
+	return new_raw_count;
+}

arch/arm64/kernel/perfctr_armv8pmu.c

@@ -824,6 +824,7 @@ static void armv8pmu_handle_irq(void *priv)
 	}
 
 	if (event) {
+		ihk_mc_event_update(event);
 		ihk_mc_event_set_period(event);
 	}
 	return;

arch/x86_64/kernel/perfctr.c

@@ -513,3 +513,8 @@ int ihk_mc_event_set_period(struct mc_perf_event *event)
 {
 	return 0;
 }
+
+uint64_t ihk_mc_event_update(struct mc_perf_event *event)
+{
+	return 0;
+}