flush instruction cache at context switch time if necessary
Change-Id: Ic09415ea772a9de6dca43a98168a8346ca86d3e7
This commit is contained in:
committed by
Masamichi Takagi
parent
f0bc1a6b07
commit
2dd8687974
@@ -47,5 +47,6 @@ static inline unsigned long read_tsc(void)
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WRITE_ONCE(*p, v); \
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})
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void arch_flush_icache_all(void);
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#endif /* ARCH_CPU_H */
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