modify file names and create directories

2012-12-17 15:39:24 +09:00
parent 9849cf57b1
commit 158903c7b6
61 changed files with 5542 additions and 0 deletions
--- a/arch/x86/elfboot/Makefile
+++ b/arch/x86/elfboot/Makefile
@@ -0,0 +1,28 @@
+CFLAGS=-c -Wall -O
+CFLAGS_TEST=-DTEST
+
+all: elfboot elfboot_test
+
+elfboot: elfboot.bin
+	cp $^ $@
+	truncate -s $(shell expr '(' `stat -c '%s' $^` + 4095 ')' / 4096 '*' 4096) $@
+
+elfboot.bin: elfboot.elf
+	objcopy -O binary $^ $@
+
+elfboot.elf: head.o elfboot.raw.o raw.lds
+	ld $(LDFLAGS_RAW) -T raw.lds -o $@ $^
+
+elfboot_test: elfboot.test.o test_main.o
+	gcc $(LDFLAGS) -o $@ $^
+
+elfboot.raw.o: elfboot.c
+	gcc $(CFLAGS) -o $@ $^
+elfboot.test.o: elfboot.c
+	gcc $(CFLAGS) $(CFLAGS_TEST) -o $@ $^
+
+clean:
+	$(RM) elfboot *.bin *.elf elfboot_test *.o
+
+disas:
+	objdump -b binary -m i386:x86-64 -D elfboot.bin
--- a/arch/x86/elfboot/elfboot.c
+++ b/arch/x86/elfboot/elfboot.c
@@ -0,0 +1,84 @@
+#include <elf.h>
+#include "test.h"
+
+#ifdef TEST
+static void *memcpy(void *dest, void *src, unsigned long len)
+{
+	dprintf("Copying %p to %p for %08ld bytes\n", src, dest, len);
+
+	return dest;
+}
+static void *memset(void *dest, int v, unsigned long len)
+{
+	dprintf("Filling %p with %02x for %08ld bytes\n", dest, (unsigned char)v, len);
+
+	return dest;
+}
+#else
+static void *memcpy(void *dest, void *src, unsigned long len)
+{
+	char *d = dest, *s = src;
+
+	for ( ; len ; len--) {
+		*(d++) = *(s++);
+	}
+
+	return d;
+}
+static void *memset(void *dest, int v, unsigned long len)
+{
+	char *d = dest;
+
+	for ( ; len ; len--) {
+		*(d++) = (char)v;
+	}
+
+	return d;
+}
+#endif
+
+static void load_programs(unsigned char *image, Elf64_Phdr *hdrs, int nhdr)
+{
+	int i;
+
+	for (i = 0; i < nhdr; i++) {
+		if (hdrs[i].p_type == PT_LOAD) {
+			dprintf("PT_LOAD : %lx: %lx - %lx (%lx)\n",
+			        hdrs[i].p_vaddr,
+			        hdrs[i].p_offset, hdrs[i].p_filesz,
+			        hdrs[i].p_memsz);
+
+			memcpy((void *)hdrs[i].p_vaddr,
+			       image + hdrs[i].p_offset,
+			       hdrs[i].p_filesz);
+			if (hdrs[i].p_filesz < hdrs[i].p_memsz) {
+				memset((void *)hdrs[i].p_vaddr + 
+				       hdrs[i].p_filesz, 0,
+				       hdrs[i].p_memsz - hdrs[i].p_filesz);
+			}
+		}
+	}
+}
+
+
+/*
+ * Return value: If success, the entry point address. Otherwise, 0.
+ */
+unsigned long elfboot_main(unsigned char *image)
+{
+	Elf64_Ehdr *hdr;
+
+	hdr = (Elf64_Ehdr *)image;
+	if (hdr->e_ident[0] != 0x7f || hdr->e_ident[1] != 'E'
+	    || hdr->e_ident[2] != 'L' || hdr->e_ident[3] != 'F') {
+		return 0;
+	}
+	/* TODO: We may overlap. So copying should be more sophisticated */
+	if (!hdr->e_phoff || hdr->e_phentsize != sizeof(Elf64_Phdr)) {
+		return 0;
+	}
+	load_programs(image, 
+	              (Elf64_Phdr *)(image + hdr->e_phoff), hdr->e_phnum);
+	return hdr->e_entry;
+}
+
--- a/arch/x86/elfboot/head.S
+++ b/arch/x86/elfboot/head.S
@@ -0,0 +1,23 @@
+.text
+.globl _start
+_start:	
+		leaq _stack_end(%rip), %rsp
+		/* preserve arguments */
+		pushq %rdi
+		pushq %rsi
+		pushq %rdx
+		pushq %rcx
+		leaq _stack_end(%rip), %rdi
+		call elfboot_main
+		andq %rax, %rax
+		jz   1f
+		popq %rcx
+		popq %rdx
+		popq %rsi
+		popq %rdi
+		jmpq *%rax				
+1:		
+		cli
+		hlt
+		jmp 1b
+		
--- a/arch/x86/elfboot/raw.lds
+++ b/arch/x86/elfboot/raw.lds
@@ -0,0 +1,37 @@
+ENTRY(_start)
+
+PHDRS
+{
+	text PT_LOAD;
+	data PT_LOAD;
+}
+
+SECTIONS
+{
+	. = SIZEOF_HEADERS;
+    . = ALIGN(4096);
+	.text :	{
+	      *(.text)
+	} :text
+	.data : {
+	      *(.data)
+	      *(.data.*)
+	} :data
+	.rodata : {
+	      *(.rodata .rodata.*)
+	} :data
+
+	. = ALIGN(8);
+	.bss : {
+	     _bss_start = .;
+	     *(.bss .bss.*)
+	     _bss_end = .;
+         . = ALIGN(4096);
+         _stack_end = .;
+    } :data
+
+	/DISCARD/ : {
+	     *(.eh_frame)
+         *(.note.gnu.build-id)
+	}
+}
--- a/arch/x86/elfboot/test.h
+++ b/arch/x86/elfboot/test.h
@@ -0,0 +1,9 @@
+#ifdef TEST
+#include <stdio.h>
+#include <stdlib.h>
+
+#define dprintf printf
+#else
+#define dprintf(...)
+#endif
+
--- a/arch/x86/elfboot/test_main.c
+++ b/arch/x86/elfboot/test_main.c
@@ -0,0 +1,41 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+
+unsigned long elfboot_main(unsigned char *image);
+
+int main(int argc, char **argv)
+{
+	int fd;
+	struct stat st;
+	void *p;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage : %s (elf)\n", argv[0]);
+		return 1;
+	}
+	fd = open(argv[1], O_RDONLY);
+	if (fd < 0){ 
+		perror("open");
+		return 1;
+	}
+
+	fstat(fd, &st);
+	
+	p = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
+	if (p == MAP_FAILED) {
+		perror("mmap");
+		return 2;
+	}
+
+	printf("read result : %lx\n", elfboot_main(p));
+
+	munmap(p, st.st_size);
+	close(fd);
+
+	return 0;
+}
--- a/arch/x86/kboot/Makefile
+++ b/arch/x86/kboot/Makefile
@@ -0,0 +1,27 @@
+DEST=$(O)/kboot
+OBJS=$(DEST)/main.o $(DEST)/data.o
+CFLAGS=-mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mcmodel=large
+
+$(if $(O),,$(error Specify the target directory))
+
+$(DEST)/kboot.elf: $(DEST) $(DEST)/kernel.lds $(OBJS)
+	@$(LD) $(LDFLAGS) -o $@ -T $(DEST)/kernel.lds -nostdlib $(OBJS)
+
+$(DEST)/%.o: %.c
+	@$(CC) $(CFLAGS) -c -o $@ -O3 $<
+
+$(DEST)/data.o: data.S
+	@$(CC) -c -o $@ -O3 -DKIMAGE='"$(KIMAGE)"' $^
+
+$(DEST)/kernel.lds: kernel.lds.S
+	$(if $(LOAD_PA),,$(error Specify the loading physical address))
+	@$(CC) -E -P -DLOAD_PA=$(LOAD_PA) -o $@ $<
+
+$(DEST):
+	@mkdir -p $(DEST)
+
+clean:
+	@$(RM) $(DEST)/*
+
+.PHONY: clean
+
--- a/arch/x86/kboot/data.S
+++ b/arch/x86/kboot/data.S
@@ -0,0 +1,9 @@
+#ifndef KIMAGE
+#error "No kernel image is specified"
+#endif
+
+.data
+.globl data_start
+data_start:
+.incbin KIMAGE
+
--- a/arch/x86/kboot/kernel.lds.S
+++ b/arch/x86/kboot/kernel.lds.S
@@ -0,0 +1,34 @@
+ENTRY(main)
+PHDRS 
+{
+	text PT_LOAD FLAGS(5);
+    data PT_LOAD FLAGS(7);
+}
+SECTIONS
+{
+	. = LOAD_PA;
+    _head = .;
+
+    .text : {
+        *(.text);
+    } : text
+
+    . = ALIGN(4096);
+	.data : {
+	      *(.data)
+	      *(.data.*)
+	} :data
+	.rodata : {
+	      *(.rodata .rodata.*)
+	} :data
+    .bss : {
+          *(.bss .bss.*)
+    }
+    . = ALIGN(4096);
+    data_end = .;
+
+	/DISCARD/ : {
+	     *(.eh_frame)
+         *(.note.gnu.build-id)
+	}
+}
--- a/arch/x86/kboot/main.c
+++ b/arch/x86/kboot/main.c
@@ -0,0 +1,132 @@
+#include <elf.h>
+
+extern char data_start[], data_end[];
+
+#define LARGE_PAGE_SIZE  (1UL << 21)
+#define LARGE_PAGE_MASK  (~((unsigned long)LARGE_PAGE_SIZE - 1))
+
+#define MAP_ST_START       0xffff800000000000UL
+#define MAP_KERNEL_START   0xffffffff80000000UL
+
+#define PTL4_SHIFT         39
+#define PTL3_SHIFT         30
+#define PTL2_SHIFT         21
+
+unsigned long page_tables[3][512] __attribute__((aligned(4096)));
+
+static void *memcpy(void *dest, void *src, unsigned long len)
+{
+	char *d = dest, *s = src;
+
+	for ( ; len ; len--) {
+		*(d++) = *(s++);
+	}
+
+	return d;
+}
+static void *memset(void *dest, int v, unsigned long len)
+{
+	char *d = dest;
+
+	for ( ; len ; len--) {
+		*(d++) = (char)v;
+	}
+
+	return d;
+}
+
+void memzerol(unsigned long *p, unsigned long size)
+{
+	unsigned long i;
+
+	size /= sizeof(unsigned long);
+
+	for (i = 0; i < size; i++) {
+		p[i] = 0;
+	}
+}
+
+static unsigned long load_programs(unsigned char *image, Elf64_Phdr *hdrs,
+                                   int nhdr, unsigned long offset)
+{
+	int i;
+	unsigned long end = MAP_KERNEL_START;
+
+	for (i = 0; i < nhdr; i++) {
+		if (hdrs[i].p_type == PT_LOAD) {
+			memcpy((void *)(hdrs[i].p_vaddr - offset),
+			       image + hdrs[i].p_offset,
+			       hdrs[i].p_filesz);
+			if (hdrs[i].p_filesz < hdrs[i].p_memsz) {
+				memset((void *)(hdrs[i].p_vaddr + 
+				                hdrs[i].p_filesz - offset), 0,
+				       hdrs[i].p_memsz - hdrs[i].p_filesz);
+			}
+			if (end < hdrs[i].p_vaddr + hdrs[i].p_memsz) {
+				end = hdrs[i].p_vaddr + hdrs[i].p_memsz;
+			}
+		}
+	}
+
+	return end;
+}
+
+/*
+ * Return value: If success, the entry point address. Otherwise, 0.
+ */
+unsigned long load_elf(unsigned char *image, unsigned long offset)
+{
+	Elf64_Ehdr *hdr = (Elf64_Ehdr *)image;
+
+	if (hdr->e_ident[0] != 0x7f || hdr->e_ident[1] != 'E'
+	    || hdr->e_ident[2] != 'L' || hdr->e_ident[3] != 'F') {
+		return 0;
+	}
+	/* TODO: We may overlap. So copying should be more sophisticated */
+	if (!hdr->e_phoff || hdr->e_phentsize != sizeof(Elf64_Phdr)) {
+		return 0;
+	}
+	return load_programs(image,
+	                     (Elf64_Phdr *)(image + hdr->e_phoff), hdr->e_phnum,
+	                     offset);
+}
+
+void main(unsigned long param)
+{
+	/* Assume phys == virt */
+	unsigned long load_address, end, *org_cr3;
+	unsigned long i, n;
+	Elf64_Ehdr *hdr;
+	void (*entry)(unsigned long param, unsigned long load_address);
+
+	load_address = (unsigned long)data_end;
+	load_address = (load_address + LARGE_PAGE_SIZE - 1) & LARGE_PAGE_MASK;
+
+	asm volatile("movq %%cr3, %0" : "=r"(org_cr3));
+
+	memzerol((unsigned long *)page_tables, sizeof(page_tables));
+
+	page_tables[0][0] = org_cr3[0];
+	page_tables[0][(MAP_ST_START >> PTL4_SHIFT) & 511] = org_cr3[0];
+	page_tables[0][(MAP_KERNEL_START >> PTL4_SHIFT) & 511] = 
+		((unsigned long)page_tables[1]) | 3;
+	page_tables[1][(MAP_KERNEL_START >> PTL3_SHIFT) & 511] = 
+		((unsigned long)page_tables[2]) | 3;
+
+	end = load_elf(data_start, MAP_KERNEL_START - load_address);
+
+	/* map 4MB more in case */
+	n = (end - MAP_KERNEL_START + (1 << PTL2_SHIFT) - 1) >> PTL2_SHIFT;
+	n += 2;
+
+	for (i = 0; i < n; i++) {
+		page_tables[2][i] = (load_address + (i << PTL2_SHIFT)) | 0x83;
+	}
+
+	hdr = (Elf64_Ehdr *)data_start;
+
+	asm volatile("movq %0, %%cr3" : : "r"(page_tables) : "memory");
+	
+	entry = (void *)hdr->e_entry;
+	entry(param, load_address);
+}
--- a/arch/x86/kernel/context.S
+++ b/arch/x86/kernel/context.S
@@ -0,0 +1,38 @@
+#define X86_CPU_LOCAL_OFFSET_TSS    128
+#define X86_TSS_OFFSET_SP0          4
+#define X86_CPU_LOCAL_OFFSET_SP0 \
+		(X86_CPU_LOCAL_OFFSET_TSS + X86_TSS_OFFSET_SP0)
+
+.text
+.globl aal_mc_switch_context
+aal_mc_switch_context:
+		pushfq
+		popq	%rax
+		testq	%rdi, %rdi
+		jz		1f				/* skip saving if "old_ctx" is null. */
+		movq	%rbp, 8(%rdi)
+		movq	%rbx, 16(%rdi)
+		movq	%rax, 72(%rdi)	/* rflags */
+		movq	%rsi, 24(%rdi)
+		movq	%rdi, 32(%rdi)
+		movq	%r12, 40(%rdi)
+		movq	%r13, 48(%rdi)
+		movq	%r14, 56(%rdi)
+		movq	%r15, 64(%rdi)
+		movq	%rsp, 0(%rdi)
+1:
+		movq	0(%rsi), %rsp
+		movq	80(%rsi), %rbp
+		movq	%rbp, %gs:(X86_CPU_LOCAL_OFFSET_SP0)
+		movq	64(%rsi), %r15
+		movq	56(%rsi), %r14
+		movq	48(%rsi), %r13
+		movq	40(%rsi), %r12
+		movq	32(%rsi), %rdi
+		movq	16(%rsi), %rbx
+		movq	72(%rsi), %rax
+		pushq	%rax
+		popfq
+		movq	8(%rsi), %rbp
+		movq	24(%rsi), %rsi
+		retq
--- a/arch/x86/kernel/cpu.c
+++ b/arch/x86/kernel/cpu.c
@@ -0,0 +1,665 @@
+#include <aal/cpu.h>
+#include <aal/debug.h>
+#include <types.h>
+#include <errno.h>
+#include <list.h>
+#include <memory.h>
+#include <string.h>
+#include <registers.h>
+#include <cpulocal.h>
+#include <march.h>
+
+#define LAPIC_ID            0x020
+#define LAPIC_TIMER         0x320
+#define LAPIC_TIMER_INITIAL 0x380
+#define LAPIC_TIMER_CURRENT 0x390
+#define LAPIC_TIMER_DIVIDE  0x3e0
+#define LAPIC_SPURIOUS      0x0f0
+#define LAPIC_EOI           0x0b0
+#define LAPIC_ICR0          0x300
+#define LAPIC_ICR2          0x310
+#define LAPIC_ESR           0x280
+
+#define APIC_INT_LEVELTRIG      0x08000
+#define APIC_INT_ASSERT         0x04000
+#define APIC_ICR_BUSY           0x01000
+#define APIC_DEST_PHYSICAL      0x00000
+#define APIC_DM_FIXED           0x00000
+#define APIC_DM_NMI             0x00400
+#define APIC_DM_INIT            0x00500
+#define APIC_DM_STARTUP         0x00600
+
+
+#define DEBUG_PRINT_CPU
+
+#ifdef DEBUG_PRINT_CPU
+#define dkprintf kprintf
+#else
+#define dkprintf(...)
+#endif
+
+
+struct x86_cpu_local_variables *get_x86_this_cpu_local(void);
+void *get_x86_this_cpu_kstack(void);
+void init_processors_local(int max_id);
+void assign_processor_id(void);
+void arch_delay(int);
+void x86_set_warm_reset(void);
+void x86_init_perfctr(void);
+
+extern int kprintf(const char *format, ...);
+
+static struct idt_entry{
+	uint32_t desc[4];
+} idt[256] __attribute__((aligned(16)));
+
+static struct x86_desc_ptr idt_desc, gdt_desc;
+
+static uint64_t gdt[] __attribute__((aligned(16))) = {
+	0,                  /* 0 */
+	0,                  /* 8 */
+	0,                  /* 16 */
+	0,                  /* 24 */
+	0x00af9b000000ffff, /* 32 : KERNEL_CS */
+	0x00cf93000000ffff, /* 40 : KERNEL_DS */
+	0x00affb000000ffff, /* 48 : USER_CS */
+	0x00aff3000000ffff, /* 56 : USER_DS */
+	0x0000890000000067, /* 64 : TSS */
+	0,                  /* (72: TSS) */
+};
+
+struct tss64 tss __attribute__((aligned(16)));
+
+static void set_idt_entry(int idx, unsigned long addr)
+{
+	idt[idx].desc[0] = (addr & 0xffff) | (KERNEL_CS << 16);
+	idt[idx].desc[1] = (addr & 0xffff0000) | 0x8e00;
+	idt[idx].desc[2] = (addr >> 32);
+	idt[idx].desc[3] = 0;
+}
+
+static void set_idt_entry_trap_gate(int idx, unsigned long addr)
+{
+	idt[idx].desc[0] = (addr & 0xffff) | (KERNEL_CS << 16);
+	idt[idx].desc[1] = (addr & 0xffff0000) | 0xef00;
+	idt[idx].desc[2] = (addr >> 32);
+	idt[idx].desc[3] = 0;
+}
+
+extern uint64_t generic_common_handlers[];
+
+void reload_idt(void)
+{
+	asm volatile("lidt %0" : : "m"(idt_desc) : "memory");
+}
+
+static struct list_head handlers[256 - 32];
+extern char page_fault[], general_protection_exception[];
+
+static void init_idt(void)
+{
+	int i;
+
+	idt_desc.size = sizeof(idt) - 1;
+	idt_desc.address = (unsigned long)idt;
+        
+	for (i = 0; i < 256; i++) {
+		if (i >= 32) {
+			INIT_LIST_HEAD(&handlers[i - 32]);
+		}
+		set_idt_entry(i, generic_common_handlers[i]);
+	}
+
+	set_idt_entry(13, (unsigned long)general_protection_exception);
+	set_idt_entry(14, (unsigned long)page_fault);
+
+	reload_idt();
+}
+
+void init_fpu(void)
+{
+	unsigned long reg;
+
+	asm volatile("movq %%cr0, %0" : "=r"(reg));
+	/* Unset EM and TS flag. */
+	reg &= ~((1 << 2) | (1 << 3));
+	/* Set MP flag */
+	reg |= 1 << 1;
+	asm volatile("movq %0, %%cr0" : : "r"(reg));
+
+#ifdef ENABLE_SSE
+	asm volatile("movq %%cr4, %0" : "=r"(reg));
+	/* Set OSFXSR flag. */
+	reg |= (1 << 9);
+	asm volatile("movq %0, %%cr4" : : "r"(reg));
+#endif
+
+	asm volatile("finit");
+}
+
+void reload_gdt(struct x86_desc_ptr *gdt_ptr)
+{
+	asm volatile("pushq %1\n"
+	             "leaq 1f(%%rip), %%rbx\n"
+	             "pushq %%rbx\n"
+	             "lgdt %0\n"
+	             "lretq\n"
+	             "1:\n" : :
+	             "m" (*gdt_ptr),
+	             "i" (KERNEL_CS) : "rbx");
+	asm volatile("movl %0, %%ds" : : "r"(KERNEL_DS));
+	asm volatile("movl %0, %%ss" : : "r"(KERNEL_DS));
+	/* And, set TSS */
+	asm volatile("ltr %0" : : "r"((short)GLOBAL_TSS) : "memory");
+}
+
+void init_gdt(void)
+{
+	register unsigned long stack_pointer asm("rsp");
+	unsigned long tss_addr = (unsigned long)&tss;
+
+	memset(&tss, 0, sizeof(tss));
+	tss.rsp0 = stack_pointer;
+        
+	/* 0x89 = Present (8) | Type = 9 (TSS) */
+	gdt[GLOBAL_TSS_ENTRY] = (sizeof(tss) - 1) 
+		| ((tss_addr & 0xffffff) << 16)
+		| (0x89UL << 40) | ((tss_addr & 0xff000000) << 32);
+	gdt[GLOBAL_TSS_ENTRY + 1] = (tss_addr >> 32);
+
+	gdt_desc.size = sizeof(gdt) - 1;
+	gdt_desc.address = (unsigned long)gdt;
+        
+	/* Load the new GDT, and set up CS, DS and SS. */
+	reload_gdt(&gdt_desc);
+}
+
+static void *lapic_vp;
+void lapic_write(int reg, unsigned int value)
+{
+	*(volatile unsigned int *)((char *)lapic_vp + reg) = value;
+}
+
+unsigned int lapic_read(int reg)
+{
+	return *(volatile unsigned int *)((char *)lapic_vp + reg);
+}
+
+void lapic_icr_write(unsigned int h, unsigned int l)
+{
+	lapic_write(LAPIC_ICR2, (unsigned int)h);
+	lapic_write(LAPIC_ICR0, l);
+}
+
+void init_lapic(void)
+{
+	unsigned long baseaddr;
+
+	/* Enable Local APIC */
+	baseaddr = rdmsr(MSR_IA32_APIC_BASE);
+	if (!lapic_vp) {
+		lapic_vp = map_fixed_area(baseaddr & PAGE_MASK, PAGE_SIZE, 1);
+	}
+	baseaddr |= 0x800;
+	wrmsr(MSR_IA32_APIC_BASE, baseaddr);
+
+	lapic_write(LAPIC_SPURIOUS, 0x1ff);
+}
+
+void lapic_ack(void)
+{
+	lapic_write(LAPIC_EOI, 0);
+}
+
+static void set_kstack(unsigned long ptr)
+{
+	struct x86_cpu_local_variables *v;
+
+	v = get_x86_this_cpu_local();
+	v->kernel_stack = ptr;
+	v->tss.rsp0 = ptr;
+}
+
+static void init_smp_processor(void)
+{
+	struct x86_cpu_local_variables *v;
+	unsigned long tss_addr;
+
+	v = get_x86_this_cpu_local();
+	tss_addr = (unsigned long)&v->tss;
+
+	v->apic_id = lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT;
+
+	memcpy(v->gdt, gdt, sizeof(v->gdt));
+	
+	memset(&v->tss, 0, sizeof(v->tss));
+
+	v->gdt[GLOBAL_TSS_ENTRY] = (sizeof(v->tss) - 1) 
+		| ((tss_addr & 0xffffff) << 16)
+		| (0x89UL << 40) | ((tss_addr & 0xff000000) << 32);
+	v->gdt[GLOBAL_TSS_ENTRY + 1] = (tss_addr >> 32);
+
+	v->gdt_ptr.size = sizeof(v->gdt) - 1;
+	v->gdt_ptr.address = (unsigned long)v->gdt;
+        
+	/* Load the new GDT, and set up CS, DS and SS. */
+	reload_gdt(&v->gdt_ptr);
+
+	set_kstack((unsigned long)get_x86_this_cpu_kstack());
+}
+
+static char *trampoline_va, *first_page_va;
+
+void aal_mc_init_ap(void)
+{
+	struct aal_mc_cpu_info *cpu_info = aal_mc_get_cpu_info();
+
+	trampoline_va = map_fixed_area(AP_TRAMPOLINE, AP_TRAMPOLINE_SIZE,
+	                               0);
+	first_page_va = map_fixed_area(0, PAGE_SIZE, 0);
+
+	kprintf("# of cpus : %d\n", cpu_info->ncpus);
+	init_processors_local(cpu_info->ncpus);
+
+	/* Do initialization for THIS cpu (BSP) */
+	assign_processor_id();
+
+	init_smp_processor();
+}
+
+extern void init_page_table(void);
+
+extern char x86_syscall[];
+long (*__x86_syscall_handler)(int, aal_mc_user_context_t *);
+
+void init_syscall(void)
+{
+	unsigned long r;
+
+	r = rdmsr(MSR_EFER);
+	r |= 1; /* SYSCALL Enable */
+	wrmsr(MSR_EFER, r);
+
+	r = (((unsigned long)KERNEL_CS) << 32) 
+		| (((unsigned long)USER_CS) << 48);
+	wrmsr(MSR_STAR, r);
+	
+	wrmsr(MSR_LSTAR, (unsigned long)x86_syscall);
+}
+
+void init_cpu(void)
+{
+	init_fpu();
+	init_lapic();
+	init_syscall();
+	x86_init_perfctr();
+}
+
+void setup_x86(void)
+{
+	cpu_disable_interrupt();
+
+	init_idt();
+
+	init_gdt();
+
+	init_page_table();
+
+	init_cpu();
+
+	kprintf("setup_x86 done.\n");
+}
+
+static volatile int cpu_boot_status;
+
+void call_ap_func(void (*next_func)(void))
+{
+	cpu_boot_status = 1;
+	next_func();
+}
+
+void setup_x86_ap(void (*next_func)(void))
+{
+	unsigned long rsp;
+	cpu_disable_interrupt();
+
+	assign_processor_id();
+
+	init_smp_processor();
+
+	reload_idt();
+
+	init_cpu();
+
+	rsp = (unsigned long)get_x86_this_cpu_kstack();
+
+	asm volatile("movq %0, %%rdi\n"
+	             "movq %1, %%rsp\n"
+	             "call *%2" : : "r"(next_func), "r"(rsp), "r"(call_ap_func)
+	             : "rdi");
+	while(1);
+}
+
+void arch_show_interrupt_context(const void *reg);
+
+void handle_interrupt(int vector, struct x86_regs *regs)
+{
+	struct aal_mc_interrupt_handler *h;
+
+	dkprintf("CPU[%d] got interrupt, vector: %d, RIP: 0x%lX\n", 
+	         aal_mc_get_processor_id(), vector, regs->rip);
+
+	if (vector < 0 || vector > 255) {
+		panic("Invalid interrupt vector.");
+	} else if (vector < 32) {
+		if (vector == 8 || 
+		    (vector >= 10 && vector <= 15) || vector == 17) {
+			kprintf("Exception %d, rflags: 0x%lX CS: 0x%lX, RIP: 0x%lX\n",
+			        vector, regs->rflags, regs->cs, regs->rip);
+		} else {
+			kprintf("Exception %d, rflags: 0x%lX CS: 0x%lX, RIP: 0x%lX\n",
+			        vector, regs->rflags, regs->cs, regs->rip);
+		}
+		arch_show_interrupt_context(regs);
+		panic("Unhandled exception");
+	} else {
+		list_for_each_entry(h, &handlers[vector - 32], list) {
+			if (h->func) {
+				h->func(h->priv);
+			}
+		}
+	}
+
+	lapic_ack();
+}
+
+void gpe_handler(struct x86_regs *regs)
+{
+	kprintf("General protection fault (err: %lx, %lx:%lx)\n",
+	        regs->error, regs->cs, regs->rip);
+	arch_show_interrupt_context(regs);
+	panic("GPF");
+}
+
+void x86_issue_ipi(unsigned int apicid, unsigned int low)
+{
+	lapic_icr_write(apicid << LAPIC_ICR_ID_SHIFT, low);
+}
+
+static void outb(uint8_t v, uint16_t port)
+{
+	asm volatile("outb %0, %1" : : "a" (v), "d" (port));
+}
+
+static void set_warm_reset_vector(unsigned long ip)
+{
+	/* Write CMOS */
+	x86_set_warm_reset();
+
+	/* Set vector */
+	*(unsigned short *)(first_page_va + 0x469) = (ip >> 4);
+	*(unsigned short *)(first_page_va + 0x467) = ip & 0xf;
+}
+
+static void wait_icr_idle(void)
+{
+	while (lapic_read(LAPIC_ICR0) & APIC_ICR_BUSY) {
+		cpu_pause();
+	}
+}
+
+static void __x86_wakeup(int apicid, unsigned long ip)
+{
+	int retry = 3;
+
+	set_warm_reset_vector(ip);
+
+	/* Clear the error */
+	lapic_write(LAPIC_ESR, 0);
+	lapic_read(LAPIC_ESR);
+
+	/* INIT */
+	x86_issue_ipi(apicid, 
+	              APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
+	wait_icr_idle();
+
+	x86_issue_ipi(apicid, 
+	              APIC_INT_LEVELTRIG | APIC_DM_INIT);
+	wait_icr_idle();
+
+	while (retry--) {
+		lapic_read(LAPIC_ESR);
+		x86_issue_ipi(apicid, APIC_DM_STARTUP | (ip >> 12));
+		wait_icr_idle();
+
+		arch_delay(200);
+
+		if (cpu_boot_status) 
+			break;
+	}
+}
+
+/** AAL Functions **/
+
+void cpu_halt(void)
+{
+	asm volatile("hlt");
+}
+
+void cpu_enable_interrupt(void)
+{
+	asm volatile("sti");
+}
+
+void cpu_disable_interrupt(void)
+{
+	asm volatile("cli");
+}
+
+void cpu_restore_interrupt(unsigned long flags)
+{
+	asm volatile("push %0; popf" : : "g"(flags) : "memory", "cc");
+}
+
+void cpu_pause(void)
+{
+	asm volatile("pause");
+}
+
+unsigned long cpu_disable_interrupt_save(void)
+{
+	unsigned long flags;
+
+	asm volatile("pushf; pop %0; cli" : "=r"(flags) : : "memory", "cc");
+
+	return flags;
+}
+
+int aal_mc_register_interrupt_handler(int vector,
+                                      struct aal_mc_interrupt_handler *h)
+{
+	if (vector < 32 || vector > 255) {
+		return -EINVAL;
+	}
+
+	list_add_tail(&h->list, &handlers[vector - 32]);
+
+	return 0;
+}
+int aal_mc_unregister_interrupt_handler(int vector,
+                                        struct aal_mc_interrupt_handler *h)
+{
+	list_del(&h->list);
+
+	return 0;
+}
+
+extern unsigned long __page_fault_handler_address;
+
+void aal_mc_set_page_fault_handler(void (*h)(unsigned long, void *))
+{
+	__page_fault_handler_address = (unsigned long)h;
+}
+
+extern char trampoline_code_data[], trampoline_code_data_end[];
+struct page_table *get_init_page_table(void);
+unsigned long get_transit_page_table(void);
+
+void aal_mc_boot_cpu(int cpuid, unsigned long pc)
+{
+	unsigned long *p;
+
+	p = (unsigned long *)trampoline_va;
+
+	memcpy(p, trampoline_code_data, 
+	       trampoline_code_data_end - trampoline_code_data);
+
+	p[1] = (unsigned long)virt_to_phys(get_init_page_table());
+	p[2] = (unsigned long)setup_x86_ap;
+	p[3] = pc;
+	p[6] = (unsigned long)get_transit_page_table();
+	if (!p[6]) {
+		p[6] = p[1];
+	}
+
+	cpu_boot_status = 0;
+
+	__x86_wakeup(cpuid, AP_TRAMPOLINE);
+
+	/* XXX: Time out */
+	while (!cpu_boot_status) {
+		cpu_pause();
+	}
+}
+
+void aal_mc_init_context(aal_mc_kernel_context_t *new_ctx,
+                         void *stack_pointer, void (*next_function)(void))
+{
+	unsigned long *sp;
+
+	if (!stack_pointer) {
+		stack_pointer = get_x86_this_cpu_kstack();
+	}
+
+	sp = stack_pointer;
+	memset(new_ctx, 0, sizeof(aal_mc_kernel_context_t));
+
+	/* Set the return address */
+	new_ctx->rsp = (unsigned long)(sp - 1);
+	sp[-1] = (unsigned long)next_function;
+}
+
+extern char enter_user_mode[];
+                                       
+void aal_mc_init_user_process(aal_mc_kernel_context_t *ctx,
+                              aal_mc_user_context_t **puctx,
+                              void *stack_pointer, unsigned long new_pc,
+                              unsigned long user_sp)
+{
+	char *sp;
+	aal_mc_user_context_t *uctx;
+
+	sp = stack_pointer;
+	sp -= sizeof(aal_mc_user_context_t);
+	uctx = (aal_mc_user_context_t *)sp;
+
+	*puctx = uctx;
+
+	memset(uctx, 0, sizeof(aal_mc_user_context_t));
+	uctx->cs = USER_CS;
+	uctx->rip = new_pc;
+	uctx->ss = USER_DS;
+	uctx->rsp = user_sp;
+	uctx->rflags = RFLAGS_IF;
+
+	aal_mc_init_context(ctx, sp, (void (*)(void))enter_user_mode);
+	ctx->rsp0 = (unsigned long)stack_pointer;
+}
+
+void aal_mc_modify_user_context(aal_mc_user_context_t *uctx,
+                                enum aal_mc_user_context_regtype reg,
+                                unsigned long value)
+{
+	if (reg == AAL_UCR_STACK_POINTER) {
+		uctx->rsp = value;
+	} else if (reg == AAL_UCR_PROGRAM_COUNTER) {
+		uctx->rip = value;
+	}
+}
+
+void aal_mc_print_user_context(aal_mc_user_context_t *uctx)
+{
+	kprintf("CS:RIP = %04lx:%16lx\n", uctx->cs, uctx->rip);
+	kprintf("%16lx %16lx %16lx %16lx\n%16lx %16lx %16lx\n",
+	        uctx->rax, uctx->rbx, uctx->rcx, uctx->rdx,
+	        uctx->rsi, uctx->rdi, uctx->rsp);
+}
+
+void aal_mc_set_syscall_handler(long (*handler)(int, aal_mc_user_context_t *))
+{
+	__x86_syscall_handler = handler;
+}
+
+void aal_mc_delay_us(int us)
+{
+	arch_delay(us);
+}
+
+void arch_show_interrupt_context(const void *reg)
+{
+	const struct x86_regs *regs = reg;
+	int irqflags;
+
+	irqflags = kprintf_lock();
+
+	__kprintf("CS:EIP = %4lX:%16lX\n", regs->cs, regs->rip);
+	__kprintf("             RAX              RBX              RCX              RDX\n");
+	__kprintf("%16lX %16lX %16lX %16lX\n",
+	        regs->rax, regs->rbx, regs->rcx, regs->rdx);
+	__kprintf("             RSI              RDI              RSP\n");
+	__kprintf("%16lX %16lX %16lX\n",
+	        regs->rsi, regs->rdi, regs->rsp);
+	__kprintf("              R8               R9              R10              R11\n");
+	__kprintf("%16lX %16lX %16lX %16lX\n",
+	        regs->r8, regs->r9, regs->r10, regs->r11);
+	__kprintf("              CS               SS        \n");
+	__kprintf("%16lX %16lX\n",
+	        regs->cs, regs->ss);
+	
+	kprintf_unlock(irqflags);
+}
+
+int aal_mc_arch_set_special_register(enum aal_asr_type type,
+                                     unsigned long value)
+{
+	/* GS modification is not permitted */
+	switch (type) {
+	case AAL_ASR_X86_FS:
+		wrmsr(MSR_FS_BASE, value);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+int aal_mc_arch_get_special_register(enum aal_asr_type type,
+                                     unsigned long *value)
+{
+	/* GS modification is not permitted */
+	switch (type) {
+	case AAL_ASR_X86_FS:
+		*value = rdmsr(MSR_FS_BASE);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+int aal_mc_interrupt_cpu(int cpu, int vector)
+{
+	kprintf("[%d] aal_mc_interrupt_cpu: %d\n", aal_mc_get_processor_id(), cpu);
+
+	wait_icr_idle();
+	x86_issue_ipi(cpu, vector);
+	return 0;
+}
--- a/arch/x86/kernel/include/arch-lock.h
+++ b/arch/x86/kernel/include/arch-lock.h
@@ -0,0 +1,84 @@
+/*
+ * Excerpted from Linux 3.0: arch/x86/include/asm/spinlock.h
+ */
+#ifndef __HEADER_X86_COMMON_ARCH_LOCK
+#define __HEADER_X86_COMMON_ARCH_LOCK
+
+#include <aal/cpu.h>
+
+//#define DEBUG_SPINLOCK
+
+#ifdef DEBUG_SPINLOCK
+int __kprintf(const char *format, ...);
+#endif
+
+typedef int aal_spinlock_t;
+
+#define AAL_STATIC_SPINLOCK_FUNCS
+
+static void aal_mc_spinlock_init(aal_spinlock_t *lock)
+{
+	*lock = 0;
+}
+#define SPIN_LOCK_UNLOCKED 0
+
+static unsigned long aal_mc_spinlock_lock(aal_spinlock_t *lock)
+{
+	int inc = 0x00010000;
+	int tmp;
+	unsigned long flags;
+	
+	flags = cpu_disable_interrupt_save();
+
+#if 0
+	asm volatile("lock ; xaddl %0, %1\n"
+	             "movzwl %w0, %2\n\t"
+	             "shrl $16, %0\n\t"
+	             "1:\t"
+	             "cmpl %0, %2\n\t"
+	             "je 2f\n\t"
+	             "rep ; nop\n\t"
+	             "movzwl %1, %2\n\t"
+	             "jmp 1b\n"
+	             "2:"
+	             : "+Q" (inc), "+m" (*lock), "=r" (tmp) : : "memory", "cc");
+#endif
+
+#ifdef DEBUG_SPINLOCK
+	__kprintf("[%d] trying to grab lock: 0x%lX\n", 
+	          aal_mc_get_processor_id(), lock);
+#endif
+	asm volatile("lock; xaddl %0, %1\n"
+			"movzwl %w0, %2\n\t"
+			"shrl $16, %0\n\t"
+			"1:\t"
+			"cmpl %0, %2\n\t"
+			"je 2f\n\t"
+			"rep ; nop\n\t"
+			"movzwl %1, %2\n\t"
+			/* don't need lfence here, because loads are in-order */
+			"jmp 1b\n"
+			"2:"
+			: "+r" (inc), "+m" (*lock), "=&r" (tmp)
+			:
+			: "memory", "cc");
+
+#ifdef DEBUG_SPINLOCK
+	__kprintf("[%d] holding lock: 0x%lX\n", aal_mc_get_processor_id(), lock);
+#endif
+
+	return flags;
+}
+
+static void aal_mc_spinlock_unlock(aal_spinlock_t *lock, unsigned long flags)
+{
+	asm volatile ("lock incw %0" : "+m"(*lock) : : "memory", "cc");
+
+	cpu_restore_interrupt(flags);
+#ifdef DEBUG_SPINLOCK
+	__kprintf("[%d] released lock: 0x%lX\n", aal_mc_get_processor_id(), lock);
+#endif
+}
+
+#endif
+
--- a/arch/x86/kernel/include/arch-memory.h
+++ b/arch/x86/kernel/include/arch-memory.h
@@ -0,0 +1,108 @@
+#ifndef __HEADER_X86_COMMON_ARCH_MEMORY_H
+#define __HEADER_X86_COMMON_ARCH_MEMORY_H
+
+#define KERNEL_CS_ENTRY    4
+#define KERNEL_DS_ENTRY    5
+#define USER_CS_ENTRY      6
+#define USER_DS_ENTRY      7
+#define GLOBAL_TSS_ENTRY   8
+
+#define KERNEL_CS          (KERNEL_CS_ENTRY * 8)
+#define KERNEL_DS          (KERNEL_DS_ENTRY * 8)
+#define USER_CS            (USER_CS_ENTRY * 8 + 3)
+#define USER_DS            (USER_DS_ENTRY * 8 + 3)
+#define GLOBAL_TSS         (GLOBAL_TSS_ENTRY * 8)
+
+#define PAGE_SHIFT         12
+#define PAGE_SIZE          (1UL << PAGE_SHIFT)
+#define PAGE_MASK          (~((unsigned long)PAGE_SIZE - 1))
+
+#define LARGE_PAGE_SHIFT   21
+#define LARGE_PAGE_SIZE    (1UL << LARGE_PAGE_SHIFT)
+#define LARGE_PAGE_MASK    (~((unsigned long)LARGE_PAGE_SIZE - 1))
+
+#define USER_END           0x0000800000000000UL
+#define MAP_ST_START       0xffff800000000000UL
+#define MAP_VMAP_START     0xfffff00000000000UL
+#define MAP_FIXED_START    0xffffffff70000000UL
+#define MAP_KERNEL_START   0xffffffff80000000UL
+
+#define MAP_VMAP_SIZE      0x0000000100000000UL
+
+#define KERNEL_PHYS_OFFSET MAP_ST_START
+
+#define PTL4_SHIFT         39
+#define PTL4_SIZE          (1UL << PTL4_SHIFT)
+#define PTL3_SHIFT         30
+#define PTL3_SIZE          (1UL << PTL3_SHIFT)
+#define PTL2_SHIFT         21     
+#define PTL2_SIZE          (1UL << PTL2_SHIFT)
+#define PTL1_SHIFT         12
+#define PTL1_SIZE          (1UL << PTL1_SHIFT)
+
+#define PT_ENTRIES         512
+
+#define PFL4_PRESENT    0x01
+#define PFL4_WRITABLE   0x02
+#define PFL4_USER       0x04
+
+#define PFL3_PRESENT    0x01
+#define PFL3_WRITABLE   0x02
+#define PFL3_USER       0x04
+#define PFL3_ACCESSED   0x20
+#define PFL3_DIRTY      0x40
+#define PFL3_SIZE       0x80   /* Used in 1G page */
+#define PFL3_GLOBAL     0x100
+
+#define PFL2_PRESENT    0x01
+#define PFL2_WRITABLE   0x02
+#define PFL2_USER       0x04
+#define PFL2_ACCESSED   0x20
+#define PFL2_DIRTY      0x40
+#define PFL2_SIZE       0x80   /* Used in 2M page */
+#define PFL2_GLOBAL     0x100
+#define PFL2_PWT        0x08
+#define PFL2_PCD        0x10
+
+#define PFL1_PRESENT    0x01
+#define PFL1_WRITABLE   0x02
+#define PFL1_USER       0x04
+#define PFL1_ACCESSED   0x20
+#define PFL1_DIRTY      0x40
+#define PFL1_PWT        0x08
+#define PFL1_PCD        0x10
+
+/* We allow user programs to access all the memory */
+#define PFL4_KERN_ATTR       (PFL4_PRESENT | PFL4_WRITABLE)
+#define PFL3_KERN_ATTR       (PFL3_PRESENT | PFL3_WRITABLE)
+#define PFL2_KERN_ATTR       (PFL2_PRESENT | PFL2_WRITABLE)
+#define PFL1_KERN_ATTR       (PFL1_PRESENT | PFL1_WRITABLE)
+
+/* For easy conversion, it is better to be the same as architecture's ones */
+enum aal_mc_pt_attribute {
+	PTATTR_ACTIVE     = 0x01,
+	PTATTR_WRITABLE   = 0x02,
+	PTATTR_USER       = 0x04,
+	PTATTR_LARGEPAGE  = 0x80,
+	PTATTR_UNCACHABLE = 0x10000,
+};
+
+typedef unsigned long pte_t;
+
+struct page_table;
+void set_pte(pte_t *ppte, unsigned long phys, int attr);
+pte_t *get_pte(struct page_table *pt, void *virt, int attr);
+
+void *early_alloc_page(void);
+void *get_last_early_heap(void);
+void flush_tlb(void);
+void flush_tlb_single(unsigned long addr);
+
+void *map_fixed_area(unsigned long phys, unsigned long size, int uncachable);
+
+#define AP_TRAMPOLINE       0x10000
+#define AP_TRAMPOLINE_SIZE  0x4000
+
+/* Local is cachable */
+#define AAL_IKC_QUEUE_PT_ATTR (PTATTR_WRITABLE | PTATTR_UNCACHABLE)
+#endif
--- a/arch/x86/kernel/include/bitops.h
+++ b/arch/x86/kernel/include/bitops.h
@@ -0,0 +1,15 @@
+#ifndef HEADER_X86_COMMON_BITOPS_H
+#define HEADER_X86_COMMON_BITOPS_H
+
+static inline int fls(int x)
+{
+	int r;
+	asm("bsrl %1,%0\n\t"
+	    "jnz 1f\n\t"
+	    "movl $-1,%0\n"
+	    "1:" : "=r" (r) : "rm" (x));
+
+	return r + 1;
+}
+
+#endif
--- a/arch/x86/kernel/include/cpulocal.h
+++ b/arch/x86/kernel/include/cpulocal.h
@@ -0,0 +1,39 @@
+#ifndef HEADER_X86_COMMON_CPULOCAL_H
+#define HEADER_X86_COMMON_CPULOCAL_H
+
+#include <types.h>
+#include <registers.h>
+
+/*
+ * CPU Local Page
+ * 0 -    : struct x86_cpu_local_varibles
+ * - 4096 : kernel stack
+ */
+
+#define X86_CPU_LOCAL_OFFSET_TSS    128
+#define X86_CPU_LOCAL_OFFSET_KSTACK 16
+#define X86_CPU_LOCAL_OFFSET_USTACK 24
+
+struct x86_cpu_local_variables {
+/* 0 */
+	unsigned long processor_id;
+
+	unsigned long apic_id;
+/* 16 */
+	unsigned long kernel_stack;
+	unsigned long user_stack;
+
+/* 32 */
+	struct x86_desc_ptr gdt_ptr;
+	unsigned short pad[3];
+/* 48 */
+	uint64_t gdt[10];
+/* 128 */
+	struct tss64 tss;
+
+} __attribute__((packed));
+
+struct x86_cpu_local_variables *get_x86_cpu_local_variable(int id);
+
+
+#endif
--- a/arch/x86/kernel/include/ihk/atomic.h
+++ b/arch/x86/kernel/include/ihk/atomic.h
@@ -0,0 +1,86 @@
+#ifndef HEADER_X86_COMMON_AAL_ATOMIC_H
+#define HEADER_X86_COMMON_AAL_ATOMIC_H
+ 
+typedef struct {
+	int counter;
+} aal_atomic_t;
+
+#define AAL_ATOMIC_INIT(i)	{ (i) }
+
+
+static inline int aal_atomic_read(const aal_atomic_t *v)
+{
+	return (*(volatile int *)&(v)->counter);
+}
+
+static inline void aal_atomic_set(aal_atomic_t *v, int i)
+{
+	v->counter = i;
+}
+
+static inline void aal_atomic_add(int i, aal_atomic_t *v)
+{
+	asm volatile("lock addl %1,%0"
+		     : "+m" (v->counter)
+		     : "ir" (i));
+}
+
+static inline void aal_atomic_sub(int i, aal_atomic_t *v)
+{
+	asm volatile("lock subl %1,%0"
+		     : "+m" (v->counter)
+		     : "ir" (i));
+}
+
+static inline void aal_atomic_inc(aal_atomic_t *v)
+{
+	asm volatile("lock incl %0"
+		     : "+m" (v->counter));
+}
+
+static inline void aal_atomic_dec(aal_atomic_t *v)
+{
+	asm volatile("lock decl %0"
+		     : "+m" (v->counter));
+}
+
+static inline int aal_atomic_dec_and_test(aal_atomic_t *v)
+{
+	unsigned char c;
+
+	asm volatile("lock decl %0; sete %1"
+		     : "+m" (v->counter), "=qm" (c)
+		     : : "memory");
+	return c != 0;
+}
+
+static inline int aal_atomic_inc_and_test(aal_atomic_t *v)
+{
+	unsigned char c;
+
+	asm volatile("lock incl %0; sete %1"
+		     : "+m" (v->counter), "=qm" (c)
+		     : : "memory");
+	return c != 0;
+}
+
+static inline int aal_atomic_add_return(int i, aal_atomic_t *v)
+{
+	int __i;
+
+	__i = i;
+	asm volatile("lock xaddl %0, %1"
+		     : "+r" (i), "+m" (v->counter)
+		     : : "memory");
+	return i + __i;
+}
+
+static inline int aal_atomic_sub_return(int i, aal_atomic_t *v)
+{
+	return aal_atomic_add_return(-i, v);
+}
+
+#define aal_atomic_inc_return(v)  (aal_atomic_add_return(1, v))
+#define aal_atomic_dec_return(v)  (aal_atomic_sub_return(1, v))
+
+#endif
--- a/arch/x86/kernel/include/ihk/context.h
+++ b/arch/x86/kernel/include/ihk/context.h
@@ -0,0 +1,27 @@
+#ifndef __HEADER_X86_COMMON_CONTEXT_H
+#define __HEADER_X86_COMMON_CONTEXT_H
+
+#include <registers.h>
+
+struct x86_kregs {
+	unsigned long rsp, rbp, rbx, rsi, rdi, r12, r13, r14, r15, rflags;
+	unsigned long rsp0;
+};
+
+typedef struct x86_kregs aal_mc_kernel_context_t;
+/* XXX: User context should contain floating point registers */
+typedef struct x86_regs aal_mc_user_context_t;
+
+#define aal_mc_syscall_arg0(uc) (uc)->rdi
+#define aal_mc_syscall_arg1(uc) (uc)->rsi
+#define aal_mc_syscall_arg2(uc) (uc)->rdx
+#define aal_mc_syscall_arg3(uc) (uc)->r10
+#define aal_mc_syscall_arg4(uc) (uc)->r8
+#define aal_mc_syscall_arg5(uc) (uc)->r9
+
+#define aal_mc_syscall_ret(uc)  (uc)->rax
+
+#define aal_mc_syscall_pc(uc)   (uc)->rip
+#define aal_mc_syscall_sp(uc)   (uc)->rsp
+
+#endif
--- a/arch/x86/kernel/include/ihk/ikc.h
+++ b/arch/x86/kernel/include/ihk/ikc.h
@@ -0,0 +1,11 @@
+#ifndef HEADER_X86_COMMON_AAL_IKC_H
+#define HEADER_X86_COMMON_AAL_IKC_H
+
+#include <ikc/aal.h>
+
+/* manycore side */
+int aal_mc_ikc_init_first(struct aal_ikc_channel_desc *,
+                          aal_ikc_ph_t handler);
+
+#endif
+
--- a/arch/x86/kernel/include/ihk/types.h
+++ b/arch/x86/kernel/include/ihk/types.h
@@ -0,0 +1,20 @@
+#ifndef X86_COMMON_TYPES_H
+#define X86_COMMON_TYPES_H
+
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef char               int8_t;
+typedef short              int16_t;
+typedef int                int32_t;
+typedef long long          int64_t;
+
+typedef long long          ptrdiff_t;
+typedef unsigned long long size_t;
+typedef long long          ssize_t;
+
+#define NULL ((void *)0)
+
+#endif
+
--- a/arch/x86/kernel/include/registers.h
+++ b/arch/x86/kernel/include/registers.h
@@ -0,0 +1,148 @@
+#ifndef __HEADER_X86_COMMON_REGISTERS_H
+#define __HEADER_X86_COMMON_REGISTERS_H
+
+#include <types.h>
+
+#define RFLAGS_IF      (1 << 9)
+
+#define MSR_EFER       0xc0000080
+#define MSR_STAR       0xc0000081
+#define MSR_LSTAR      0xc0000082
+#define MSR_FMASK      0xc0000084
+#define MSR_FS_BASE    0xc0000100
+#define MSR_GS_BASE    0xc0000101
+
+#define MSR_IA32_APIC_BASE 0x000000001b
+
+#define CVAL(event, mask) \
+        ((((event) & 0xf00) << 24) | ((mask) << 8) | ((event) & 0xff))
+#define CVAL2(event, mask, inv, count)    \
+        ((((event) & 0xf00) << 24) | ((mask) << 8) | ((event) & 0xff) | \
+         ((inv & 1) << 23) | ((count & 0xff) << 24))
+
+/* AMD */
+#define MSR_PERF_CTL_0 0xc0010000
+#define MSR_PERF_CTR_0 0xc0010004
+
+static void wrmsr(unsigned int idx, unsigned long value){
+	unsigned int high, low;
+
+	high = value >> 32;
+	low = value & 0xffffffffU;
+
+	asm volatile("wrmsr" : : "c" (idx), "a" (low), "d" (high) : "memory");
+}
+
+static unsigned long rdpmc(unsigned int counter)
+{
+	unsigned int high, low;
+
+	asm volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (counter));
+
+	return (unsigned long)high << 32 | low;
+}
+
+static unsigned long rdmsr(unsigned int index)
+{
+	unsigned int high, low;
+
+	asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (index));
+
+	return (unsigned long)high << 32 | low;
+}
+
+static unsigned long rdtsc(void)
+{
+	unsigned int high, low;
+
+	asm volatile("rdtsc" : "=a" (low), "=d" (high));
+
+	return (unsigned long)high << 32 | low;
+}
+
+static void set_perfctl(int counter, int event, int mask)
+{
+	unsigned long value;
+
+	value = ((unsigned long)(event & 0x700) << 32)
+		| (event & 0xff) | ((mask & 0xff) << 8) | (1 << 18)
+		 | (1 << 17);
+
+	wrmsr(MSR_PERF_CTL_0 + counter, value);
+}
+
+static void start_perfctr(int counter)
+{
+	unsigned long value;
+
+	value = rdmsr(MSR_PERF_CTL_0 + counter);
+	value |= (1 << 22);
+	wrmsr(MSR_PERF_CTL_0 + counter, value);
+}
+static void stop_perfctr(int counter)
+{
+	unsigned long value;
+
+	value = rdmsr(MSR_PERF_CTL_0 + counter);
+	value &= ~(1 << 22);
+	wrmsr(MSR_PERF_CTL_0 + counter, value);
+}
+
+static void clear_perfctl(int counter)
+{
+	wrmsr(MSR_PERF_CTL_0 + counter, 0);
+}
+
+static void set_perfctr(int counter, unsigned long value)
+{
+	wrmsr(MSR_PERF_CTR_0 + counter, value);
+}
+
+static unsigned long read_perfctr(int counter)
+{
+	return rdpmc(counter);
+}
+
+#define aal_mc_mb()   asm volatile("mfence" : : : "memory");
+
+struct x86_desc_ptr {
+        uint16_t size;
+        uint64_t address;
+} __attribute__((packed));
+
+struct tss64 {
+        unsigned int reserved0;
+        unsigned long rsp0;
+        unsigned long rsp1;
+        unsigned long rsp2;
+        unsigned int reserved1, reserved2;
+        unsigned long ist[7];
+        unsigned int reserved3, reserved4;
+        unsigned short reserved5;
+        unsigned short iomap_address;
+} __attribute__((packed));
+
+struct x86_regs {
+	unsigned long r11, r10, r9, r8;
+	unsigned long rdi, rsi, rdx, rcx, rbx, rax;
+	unsigned long error, rip, cs, rflags, rsp, ss;
+};
+
+/*
+ * Page fault error code bits:
+ *
+ *   bit 0 ==	0: no page found	1: protection fault
+ *   bit 1 ==	0: read access		1: write access
+ *   bit 2 ==	0: kernel-mode access	1: user-mode access
+ *   bit 3 ==	1: use of reserved bit detected
+ *   bit 4 ==	1: fault was an instruction fetch
+ */
+enum x86_pf_error_code {
+	PF_PROT		=		1 << 0,
+	PF_WRITE	=		1 << 1,
+	PF_USER		=		1 << 2,
+	PF_RSVD		=		1 << 3,
+	PF_INSTR	=		1 << 4,
+};
+
+#endif
--- a/arch/x86/kernel/interrupt.S
+++ b/arch/x86/kernel/interrupt.S
@@ -0,0 +1,128 @@
+#define X86_CPU_LOCAL_OFFSET_TSS    128
+#define X86_TSS_OFFSET_SP0          4
+#define X86_CPU_LOCAL_OFFSET_SP0 \
+		(X86_CPU_LOCAL_OFFSET_TSS + X86_TSS_OFFSET_SP0)
+#define X86_CPU_LOCAL_OFFSET_KSTACK 16
+#define X86_CPU_LOCAL_OFFSET_USTACK 24
+#define KERNEL_CS                   32
+#define KERNEL_DS                   40
+#define USER_CS                     (48 + 3)
+#define USER_DS                     (56 + 3)
+
+#define PUSH_ALL_REGS     \
+        pushq %rax; \
+        pushq %rbx; \
+        pushq %rcx; \
+        pushq %rdx; \
+        pushq %rsi; \
+        pushq %rdi; \
+        pushq %r8;  \
+        pushq %r9; \
+        pushq %r10; \
+        pushq %r11; 
+#define POP_ALL_REGS      \
+        popq  %r11; \
+        popq  %r10; \
+        popq  %r9;  \
+        popq  %r8;  \
+        popq  %rdi; \
+        popq  %rsi; \
+        popq  %rdx; \
+        popq  %rcx; \
+        popq  %rbx; \
+        popq  %rax
+		
+.data
+.globl generic_common_handlers
+generic_common_handlers:
+.text
+vector=0
+.rept 256
+1:      
+        cld
+		pushq   $vector
+        jmp     common_interrupt
+.previous
+        .quad   1b
+.text
+vector=vector+1
+.endr
+
+common_interrupt:
+		PUSH_ALL_REGS
+		movq    80(%rsp), %rdi
+		movq	%rsp, %rsi
+		call 	handle_interrupt /* Enter C code */
+		POP_ALL_REGS
+		addq	$8, %rsp
+		iretq
+
+.globl __page_fault_handler_address
+__page_fault_handler_address:
+		.quad	0
+
+.globl page_fault
+page_fault:
+		cld
+		PUSH_ALL_REGS
+		movq	%cr2, %rdi
+		movq	%rsp, %rsi
+		movq    %rbp, %rdx
+		movq	__page_fault_handler_address(%rip), %rax
+		andq	%rax, %rax
+		jz		1f
+		call	*%rax
+		POP_ALL_REGS
+		addq	$8, %rsp
+		iretq
+1:		
+		jmp		1b
+
+.globl general_protection_exception
+general_protection_exception:
+		cld
+		PUSH_ALL_REGS
+		movq	%rsp, %rdi
+		call	gpe_handler
+		POP_ALL_REGS
+		addq	$8, %rsp
+		iretq
+
+.globl x86_syscall
+x86_syscall:
+		cld
+		movq	%rsp, %gs:24
+		movq	%gs:(X86_CPU_LOCAL_OFFSET_SP0), %rsp
+
+		pushq	$(USER_DS)
+		pushq	$0
+		pushq	%r11
+		pushq   $(USER_CS)
+		pushq	%rcx
+		pushq	$0
+		movq	%gs:24, %rcx
+		movq	%rcx, 32(%rsp)
+		PUSH_ALL_REGS
+		movq	72(%rsp), %rdi
+		movw	%ss, %ax
+		movw	%ax, %ds
+		movq	%rsp, %rsi
+		callq	*__x86_syscall_handler(%rip)
+1:		
+		movq	%rax, 72(%rsp)
+		POP_ALL_REGS
+#ifdef USE_SYSRET
+		movq	8(%rsp), %rcx
+		movq	24(%rsp), %r11
+		movq	32(%rsp), %rsp
+		sysretq
+#else
+		addq	$8, %rsp
+		iretq
+#endif
+		
+.globl enter_user_mode
+enter_user_mode:		
+		POP_ALL_REGS
+		addq	$8, %rsp
+		iretq
--- a/arch/x86/kernel/local.c
+++ b/arch/x86/kernel/local.c
@@ -0,0 +1,85 @@
+#include <cpulocal.h>
+#include <aal/atomic.h>
+#include <aal/mm.h>
+#include <aal/cpu.h>
+#include <aal/debug.h>
+#include <registers.h>
+#include <string.h>
+
+struct x86_cpu_local_variables *locals;
+
+void init_processors_local(int max_id)
+{
+	/* Is contiguous allocating adequate?? */
+	locals = aal_mc_alloc_pages(max_id, 0);
+	memset(locals, 0, PAGE_SIZE * max_id);
+
+	kprintf("locals = %p\n", locals);
+}
+
+struct x86_cpu_local_variables *get_x86_cpu_local_variable(int id)
+{
+	return (struct x86_cpu_local_variables *)
+		((char *)locals + (id << PAGE_SHIFT));
+}
+
+static void *get_x86_cpu_local_kstack(int id)
+{
+	return ((char *)locals + ((id + 1) << PAGE_SHIFT));
+}
+
+struct x86_cpu_local_variables *get_x86_this_cpu_local(void)
+{
+	int id = aal_mc_get_processor_id();
+
+	return get_x86_cpu_local_variable(id);
+}
+
+void *get_x86_this_cpu_kstack(void)
+{
+	int id = aal_mc_get_processor_id();
+
+	return get_x86_cpu_local_kstack(id);
+}
+
+static void set_fs_base(void *address)
+{
+	wrmsr(MSR_FS_BASE, (unsigned long)address);
+}
+
+static void set_gs_base(void *address)
+{
+	wrmsr(MSR_GS_BASE, (unsigned long)address);
+}
+
+static aal_atomic_t last_processor_id = AAL_ATOMIC_INIT(-1);
+
+void assign_processor_id(void)
+{
+	int id;
+	struct x86_cpu_local_variables *v;
+
+	id = aal_atomic_inc_return(&last_processor_id);
+
+	v = get_x86_cpu_local_variable(id);
+	set_gs_base(v);
+
+	v->processor_id = id;
+}
+
+/** AAL **/
+int aal_mc_get_processor_id(void)
+{
+	int id;
+
+	asm volatile("movl %%gs:0, %0" : "=r"(id));
+
+	return id;
+}
+
+int aal_mc_get_hardware_processor_id(void)
+{
+	struct x86_cpu_local_variables *v =  get_x86_this_cpu_local();
+
+	return v->apic_id;
+}
--- a/arch/x86/kernel/lock.c
+++ b/arch/x86/kernel/lock.c
@@ -0,0 +1,35 @@
+#include <aal/lock.h>
+
+#if 0
+
+void aal_mc_spinlock_init(aal_spinlock_t *lock)
+{
+	*lock = 0;
+}
+
+void aal_mc_spinlock_lock(aal_spinlock_t *lock, unsigned long *flags)
+{
+	int inc = 0x00010000;
+	int tmp;
+	
+	cpu_disable_interrupt_save(flags);
+	asm volatile("lock ; xaddl %0, %1\n"
+	             "movzwl %w0, %2\n\t"
+	             "shrl $16, %0\n\t"
+	             "1:\t"
+	             "cmpl %0, %2\n\t"
+	             "je 2f\n\t"
+	             "rep ; nop\n\t"
+	             "movzwl %1, %2\n\t"
+	             "jmp 1b\n"
+	             "2:"
+	             : "+Q" (inc), "+m" (*lock), "=r" (tmp) : : "memory", "cc");
+}
+
+void aal_mc_spinlock_unlock(aal_spinlock_t *lock, unsigned long *flags)
+{
+	asm volatile ("lock incw %0" : "+m"(*lock) : : "memory", "cc");
+	cpu_restore_interrupt(*flags);
+}
+
+#endif
--- a/arch/x86/kernel/memory.c
+++ b/arch/x86/kernel/memory.c
@@ -0,0 +1,703 @@
+#include <aal/cpu.h>
+#include <aal/debug.h>
+#include <aal/mm.h>
+#include <types.h>
+#include <memory.h>
+#include <string.h>
+#include <errno.h>
+#include <list.h>
+
+static char *last_page;
+extern char _head[], _end[];
+
+struct aal_mc_pa_ops *pa_ops;
+
+extern unsigned long x86_kernel_phys_base;
+
+void *early_alloc_page(void)
+{
+	void *p;
+
+	if (!last_page) {
+		last_page = (char *)(((unsigned long)_end + PAGE_SIZE - 1)
+		                     & PAGE_MASK);
+		/* Convert the virtual address from text's to straight maps */
+		last_page = phys_to_virt(virt_to_phys(last_page));
+	} else if (last_page == (void *)-1) {
+		panic("Early allocator is already finalized. Do not use it.\n");
+	}
+	p = last_page;
+	last_page += PAGE_SIZE;
+
+	return p;
+}
+
+void *arch_alloc_page(enum aal_mc_ap_flag flag)
+{
+	if (pa_ops)
+		return pa_ops->alloc_page(1, flag);
+	else
+		return early_alloc_page();
+}
+void arch_free_page(void *ptr)
+{
+	if (pa_ops)
+		pa_ops->free_page(ptr, 1);
+}
+
+void *aal_mc_alloc_pages(int npages, enum aal_mc_ap_flag flag)
+{
+	if (pa_ops)
+		return pa_ops->alloc_page(npages, flag);
+	else
+		return NULL;
+}
+
+void aal_mc_free_pages(void *p, int npages)
+{
+	if (pa_ops)
+		pa_ops->free_page(p, npages);
+}
+
+void *aal_mc_allocate(int size, enum aal_mc_ap_flag flag)
+{
+	if (pa_ops && pa_ops->alloc)
+		return pa_ops->alloc(size, flag);
+	else
+		return aal_mc_alloc_pages(1, flag);
+}
+
+void aal_mc_free(void *p)
+{
+	if (pa_ops && pa_ops->free)
+		return pa_ops->free(p);
+	else
+		return aal_mc_free_pages(p, 1);
+}
+
+void *get_last_early_heap(void)
+{
+	return last_page;
+}
+
+void flush_tlb(void)
+{
+	unsigned long cr3;
+
+	asm volatile("movq %%cr3, %0; movq %0, %%cr3" : "=r"(cr3) : : "memory");
+}
+
+void flush_tlb_single(unsigned long addr)
+{
+   asm volatile("invlpg (%0)" :: "r" (addr) : "memory");
+}
+
+struct page_table {
+	pte_t entry[PT_ENTRIES];
+};
+
+static struct page_table *init_pt;
+
+static unsigned long setup_l2(struct page_table *pt,
+                              unsigned long page_head, unsigned long start,
+                              unsigned long end)
+{
+	int i;
+	unsigned long phys;
+
+	for (i = 0; i < PT_ENTRIES; i++) {
+		phys = page_head + ((unsigned long)i << PTL2_SHIFT);
+
+		if (phys + PTL2_SIZE <= start || phys >= end) {
+			pt->entry[i] = 0;
+			continue;
+		}
+
+		pt->entry[i] = phys | PFL2_KERN_ATTR | PFL2_SIZE;
+	}
+
+	return virt_to_phys(pt);
+}
+
+static unsigned long setup_l3(struct page_table *pt,
+                              unsigned long page_head, unsigned long start,
+                              unsigned long end)
+{
+	int i;
+	unsigned long phys, pt_phys;
+
+	for (i = 0; i < PT_ENTRIES; i++) {
+		phys = page_head + ((unsigned long)i << PTL3_SHIFT);
+
+		if (phys + PTL3_SIZE <= start || phys >= end) {
+			pt->entry[i] = 0;
+			continue;
+		}
+		pt_phys = setup_l2(arch_alloc_page(0), phys, start, end);
+
+		pt->entry[i] = pt_phys | PFL3_KERN_ATTR;
+	}
+
+	return virt_to_phys(pt);
+}
+
+static void init_normal_area(struct page_table *pt)
+{
+	unsigned long map_start, map_end, phys, pt_phys;
+	int ident_index, virt_index;
+
+	map_start = aal_mc_get_memory_address(AAL_MC_GMA_MAP_START, 0);
+	map_end = aal_mc_get_memory_address(AAL_MC_GMA_MAP_END, 0);
+
+	kprintf("map_start = %lx, map_end = %lx\n", map_start, map_end);
+	ident_index = map_start >> PTL4_SHIFT;
+	virt_index = (MAP_ST_START >> PTL4_SHIFT) & (PT_ENTRIES - 1);
+
+	memset(pt, 0, sizeof(struct page_table));
+
+	for (phys = (map_start & ~(PTL4_SIZE - 1)); phys < map_end;
+	     phys += PTL4_SIZE) {
+		pt_phys = setup_l3(arch_alloc_page(0), phys,
+		                   map_start, map_end);
+
+		pt->entry[ident_index++] = pt_phys | PFL4_KERN_ATTR;
+		pt->entry[virt_index++] = pt_phys | PFL4_KERN_ATTR;
+	}
+}
+
+static struct page_table *__alloc_new_pt(void)
+{
+	struct page_table *newpt = arch_alloc_page(0);
+
+	memset(newpt, 0, sizeof(struct page_table));
+
+	return newpt;
+}
+
+/*
+ * XXX: Confusingly, L4 and L3 automatically add PRESENT,
+ *      but L2 and L1 do not!
+ */
+
+#define ATTR_MASK (PTATTR_WRITABLE | PTATTR_USER | PTATTR_ACTIVE)
+static unsigned long attr_to_l4attr(enum aal_mc_pt_attribute attr)
+{
+	return (attr & ATTR_MASK) | PFL4_PRESENT;
+}
+static unsigned long attr_to_l3attr(enum aal_mc_pt_attribute attr)
+{
+	return (attr & ATTR_MASK) | PFL3_PRESENT;
+}
+static unsigned long attr_to_l2attr(enum aal_mc_pt_attribute attr)
+{
+	unsigned long r = (attr & (ATTR_MASK | PTATTR_LARGEPAGE));
+
+	if ((attr & PTATTR_UNCACHABLE) && (attr & PTATTR_LARGEPAGE)) {
+		return r | PFL2_PCD | PFL2_PWT; 
+	}
+	return r;
+}
+static unsigned long attr_to_l1attr(enum aal_mc_pt_attribute attr)
+{
+	if (attr & PTATTR_UNCACHABLE) {
+		return (attr & ATTR_MASK) | PFL1_PWT | PFL1_PWT;
+	} else { 
+		return (attr & ATTR_MASK);
+	}
+}
+
+#define GET_VIRT_INDICES(virt, l4i, l3i, l2i, l1i) \
+	l4i = ((virt) >> PTL4_SHIFT) & (PT_ENTRIES - 1); \
+	l3i = ((virt) >> PTL3_SHIFT) & (PT_ENTRIES - 1); \
+	l2i = ((virt) >> PTL2_SHIFT) & (PT_ENTRIES - 1); \
+	l1i = ((virt) >> PTL1_SHIFT) & (PT_ENTRIES - 1)
+
+
+void set_pte(pte_t *ppte, unsigned long phys, int attr)
+{
+	if (attr & PTATTR_LARGEPAGE) {
+		*ppte = phys | attr_to_l2attr(attr) | PFL2_SIZE;
+	}
+	else {
+		*ppte = phys | attr_to_l1attr(attr);
+	}
+}
+
+
+/* 
+ * get_pte() 
+ *
+ * Descripton: walks the page tables (creates tables if not existing)
+ *             and returns a pointer to the PTE corresponding to the
+ *             virtual address.
+ */
+pte_t *get_pte(struct page_table *pt, void *virt, int attr)
+{
+	int l4idx, l3idx, l2idx, l1idx;
+	unsigned long v = (unsigned long)virt;
+	struct page_table *newpt;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+
+	GET_VIRT_INDICES(v, l4idx, l3idx, l2idx, l1idx);
+
+    /* TODO: more detailed attribute check */
+	if (pt->entry[l4idx] & PFL4_PRESENT) {
+		pt = phys_to_virt(pt->entry[l4idx] & PAGE_MASK);
+	} else {
+		newpt = __alloc_new_pt();
+		pt->entry[l4idx] = virt_to_phys(newpt) | attr_to_l4attr(attr);
+		pt = newpt;
+	}
+
+	if (pt->entry[l3idx] & PFL3_PRESENT) {
+		pt = phys_to_virt(pt->entry[l3idx] & PAGE_MASK);
+	} else {
+		newpt = __alloc_new_pt();
+		pt->entry[l3idx] = virt_to_phys(newpt) | attr_to_l3attr(attr);
+		pt = newpt;
+	}
+
+	/* TODO: PTATTR_LARGEPAGE 
+	if (attr & PTATTR_LARGEPAGE) {
+		if (pt->entry[l2idx] & PFL2_PRESENT) {
+			if ((pt->entry[l2idx] & PAGE_MASK) != phys) {
+				return -EBUSY;
+			} else {
+				return 0;
+			}
+		} else {
+			pt->entry[l2idx] = phys | attr_to_l2attr(attr)
+				| PFL2_SIZE;
+			return 0;
+		}
+	}
+	*/
+
+	if (pt->entry[l2idx] & PFL2_PRESENT) {
+		pt = phys_to_virt(pt->entry[l2idx] & PAGE_MASK);
+	} else {
+		newpt = __alloc_new_pt();
+		pt->entry[l2idx] = virt_to_phys(newpt) | attr_to_l2attr(attr)
+			| PFL2_PRESENT;
+		pt = newpt;
+	}
+
+	return &(pt->entry[l1idx]);
+}
+
+static int __set_pt_page(struct page_table *pt, void *virt, unsigned long phys,
+                         int attr)
+{
+	int l4idx, l3idx, l2idx, l1idx;
+	unsigned long v = (unsigned long)virt;
+	struct page_table *newpt;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+	if (attr & PTATTR_LARGEPAGE) {
+		phys &= LARGE_PAGE_MASK;
+	} else {
+		phys &= PAGE_MASK;
+	}
+
+	GET_VIRT_INDICES(v, l4idx, l3idx, l2idx, l1idx);
+
+	/* TODO: more detailed attribute check */
+	if (pt->entry[l4idx] & PFL4_PRESENT) {
+		pt = phys_to_virt(pt->entry[l4idx] & PAGE_MASK);
+	} else {
+		newpt = __alloc_new_pt();
+		pt->entry[l4idx] = virt_to_phys(newpt) | attr_to_l4attr(attr);
+		pt = newpt;
+	}
+
+	if (pt->entry[l3idx] & PFL3_PRESENT) {
+		pt = phys_to_virt(pt->entry[l3idx] & PAGE_MASK);
+	} else {
+		newpt = __alloc_new_pt();
+		pt->entry[l3idx] = virt_to_phys(newpt) | attr_to_l3attr(attr);
+		pt = newpt;
+	}
+
+	if (attr & PTATTR_LARGEPAGE) {
+		if (pt->entry[l2idx] & PFL2_PRESENT) {
+			if ((pt->entry[l2idx] & PAGE_MASK) != phys) {
+				return -EBUSY;
+			} else {
+				return 0;
+			}
+		} else {
+			pt->entry[l2idx] = phys | attr_to_l2attr(attr)
+				| PFL2_SIZE;
+			return 0;
+		}
+	}
+
+	if (pt->entry[l2idx] & PFL2_PRESENT) {
+		pt = phys_to_virt(pt->entry[l2idx] & PAGE_MASK);
+	} else {
+		newpt = __alloc_new_pt();
+		pt->entry[l2idx] = virt_to_phys(newpt) | attr_to_l2attr(attr)
+			| PFL2_PRESENT;
+		pt = newpt;
+	}
+
+	if (pt->entry[l1idx] & PFL1_PRESENT) {
+		if ((pt->entry[l1idx] & PAGE_MASK) != phys) {
+			return -EBUSY;
+		} else {
+			return 0;
+		}
+	}
+	pt->entry[l1idx] = phys | attr_to_l1attr(attr);
+	return 0;
+}
+
+static int __clear_pt_page(struct page_table *pt, void *virt, int largepage)
+{
+	int l4idx, l3idx, l2idx, l1idx;
+	unsigned long v = (unsigned long)virt;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+	if (largepage) {
+		v &= LARGE_PAGE_MASK;
+	} else {
+		v &= PAGE_MASK;
+	}
+
+	GET_VIRT_INDICES(v, l4idx, l3idx, l2idx, l1idx);
+
+	if (!(pt->entry[l4idx] & PFL4_PRESENT)) {
+		return -EINVAL;
+	}
+	pt = phys_to_virt(pt->entry[l4idx] & PAGE_MASK);
+
+	if (!(pt->entry[l3idx] & PFL3_PRESENT)) {
+		return -EINVAL;
+	}
+	pt = phys_to_virt(pt->entry[l3idx] & PAGE_MASK);
+
+	if (largepage) {
+		if (!(pt->entry[l2idx] & PFL2_PRESENT)) {
+			return -EINVAL;
+		} else {
+			pt->entry[l2idx] = 0;
+			return 0;
+		}
+	}
+	pt = phys_to_virt(pt->entry[l2idx] & PAGE_MASK);
+
+	pt->entry[l1idx] = 0;
+
+	return 0;
+}
+
+int aal_mc_pt_virt_to_phys(struct page_table *pt,
+                           void *virt, unsigned long *phys)
+{
+	int l4idx, l3idx, l2idx, l1idx;
+	unsigned long v = (unsigned long)virt;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+
+	GET_VIRT_INDICES(v, l4idx, l3idx, l2idx, l1idx);
+
+	if (!(pt->entry[l4idx] & PFL4_PRESENT)) {
+		return -EFAULT;
+	}
+	pt = phys_to_virt(pt->entry[l4idx] & PAGE_MASK);
+
+	if (!(pt->entry[l3idx] & PFL3_PRESENT)) {
+		return -EFAULT;
+	}
+	pt = phys_to_virt(pt->entry[l3idx] & PAGE_MASK);
+
+	if (!(pt->entry[l2idx] & PFL2_PRESENT)) {
+		return -EFAULT;
+	}
+	if ((pt->entry[l2idx] & PFL2_SIZE)) {
+		*phys = (pt->entry[l2idx] & LARGE_PAGE_MASK) | 
+			(v & (LARGE_PAGE_SIZE - 1));
+		return 0;
+	}
+	pt = phys_to_virt(pt->entry[l2idx] & PAGE_MASK);
+
+	if (!(pt->entry[l1idx] & PFL1_PRESENT)) {
+		return -EFAULT;
+	}
+
+	*phys = (pt->entry[l1idx] & PAGE_MASK) | (v & (PAGE_SIZE - 1));
+	return 0;
+}
+
+int aal_mc_pt_print_pte(struct page_table *pt, void *virt)
+{
+	int l4idx, l3idx, l2idx, l1idx;
+	unsigned long v = (unsigned long)virt;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+
+	GET_VIRT_INDICES(v, l4idx, l3idx, l2idx, l1idx);
+
+	if (!(pt->entry[l4idx] & PFL4_PRESENT)) {
+		__kprintf("0x%lX l4idx not present! \n", (unsigned long)virt);
+		return -EFAULT;
+	}
+	pt = phys_to_virt(pt->entry[l4idx] & PAGE_MASK);
+
+	__kprintf("l3 table: 0x%lX l3idx: %d \n", virt_to_phys(pt), l3idx);
+	if (!(pt->entry[l3idx] & PFL3_PRESENT)) {
+		__kprintf("0x%lX l3idx not present! \n", (unsigned long)virt);
+		return -EFAULT;
+	}
+	pt = phys_to_virt(pt->entry[l3idx] & PAGE_MASK);
+	
+	__kprintf("l2 table: 0x%lX l2idx: %d \n", virt_to_phys(pt), l2idx);
+	if (!(pt->entry[l2idx] & PFL2_PRESENT)) {
+		__kprintf("0x%lX l2idx not present! \n", (unsigned long)virt);
+		return -EFAULT;
+	}
+	if ((pt->entry[l2idx] & PFL2_SIZE)) {
+		return 0;
+	}
+	pt = phys_to_virt(pt->entry[l2idx] & PAGE_MASK);
+
+	__kprintf("l1 table: 0x%lX l1idx: %d \n", virt_to_phys(pt), l1idx);
+	if (!(pt->entry[l1idx] & PFL1_PRESENT)) {
+		__kprintf("0x%lX PTE (l1) not present! entry: 0x%lX\n", 
+		          (unsigned long)virt, pt->entry[l1idx]);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+int set_pt_large_page(struct page_table *pt, void *virt, unsigned long phys,
+                      enum aal_mc_pt_attribute attr)
+{
+	return __set_pt_page(pt, virt, phys, attr | PTATTR_LARGEPAGE
+	                     | PTATTR_ACTIVE);
+}
+
+int aal_mc_pt_set_large_page(page_table_t pt, void *virt,
+                       unsigned long phys, enum aal_mc_pt_attribute attr)
+{
+	return __set_pt_page(pt, virt, phys, attr | PTATTR_LARGEPAGE
+	                     | PTATTR_ACTIVE);
+}
+
+int aal_mc_pt_set_page(page_table_t pt, void *virt,
+                       unsigned long phys, enum aal_mc_pt_attribute attr)
+{
+	return __set_pt_page(pt, virt, phys, attr | PTATTR_ACTIVE);
+}
+
+int aal_mc_pt_prepare_map(page_table_t p, void *virt, unsigned long size,
+                          enum aal_mc_pt_prepare_flag flag)
+{
+	int l4idx, l4e, ret = 0;
+	unsigned long v = (unsigned long)virt;
+	struct page_table *pt = p, *newpt;
+	unsigned long l;
+	enum aal_mc_pt_attribute attr = PTATTR_WRITABLE;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+
+	l4idx = ((v) >> PTL4_SHIFT) & (PT_ENTRIES - 1);
+
+	if (flag == AAL_MC_PT_FIRST_LEVEL) {
+		l4e = ((v + size) >> PTL4_SHIFT)  & (PT_ENTRIES - 1);
+
+		for (; l4idx <= l4e; l4idx++) {
+			if (pt->entry[l4idx] & PFL4_PRESENT) {
+				return 0;
+			} else {
+				newpt = __alloc_new_pt();
+				if (!newpt) {
+					ret = -ENOMEM;
+				} else { 
+					pt->entry[l4idx] = virt_to_phys(newpt)
+						| attr_to_l4attr(attr);
+				}
+			}
+		}
+	} else {
+		/* Call without ACTIVE flag */
+		l = v + size;
+		for (; v < l; v += PAGE_SIZE) {
+			if ((ret = __set_pt_page(pt, (void *)v, 0, attr))) {
+				break;
+			}
+		}
+	}
+	return ret;
+}
+
+struct page_table *aal_mc_pt_create(void)
+{
+	struct page_table *pt = aal_mc_alloc_pages(1, 0);
+
+	memset(pt->entry, 0, PAGE_SIZE);
+	/* Copy the kernel space */
+	memcpy(pt->entry + PT_ENTRIES / 2, init_pt->entry + PT_ENTRIES / 2,
+	       sizeof(pt->entry[0]) * PT_ENTRIES / 2);
+
+	return pt;
+}
+
+int aal_mc_pt_clear_page(page_table_t pt, void *virt)
+{
+	return __clear_pt_page(pt, virt, 0);
+}
+
+void load_page_table(struct page_table *pt)
+{
+	unsigned long pt_addr;
+
+	if (!pt) {
+		pt = init_pt;
+	}
+
+	pt_addr = virt_to_phys(pt);
+
+	asm volatile ("movq %0, %%cr3" : : "r"(pt_addr) : "memory");
+}
+
+void aal_mc_load_page_table(struct page_table *pt)
+{
+	load_page_table(pt);
+}
+
+struct page_table *get_init_page_table(void)
+{
+	return init_pt;
+}
+
+static unsigned long fixed_virt;
+static void init_fixed_area(struct page_table *pt)
+{
+	fixed_virt = MAP_FIXED_START;
+
+	return;
+}
+
+void init_text_area(struct page_table *pt)
+{
+	unsigned long __end, phys, virt;
+	int i, nlpages;
+
+	__end = ((unsigned long)_end + LARGE_PAGE_SIZE * 2 - 1)
+		& LARGE_PAGE_MASK;
+	nlpages = (__end - MAP_KERNEL_START) >> LARGE_PAGE_SHIFT;
+
+	kprintf("TEXT: # of large pages = %d\n", nlpages);
+	kprintf("TEXT: Base address = %lx\n", x86_kernel_phys_base);
+
+	phys = x86_kernel_phys_base;
+	virt = MAP_KERNEL_START;
+	for (i = 0; i < nlpages; i++) {
+		set_pt_large_page(pt, (void *)virt, phys, PTATTR_WRITABLE);
+
+		virt += LARGE_PAGE_SIZE;
+		phys += LARGE_PAGE_SIZE;
+	}
+}
+
+void *map_fixed_area(unsigned long phys, unsigned long size, int uncachable)
+{
+	unsigned long poffset, paligned;
+	int i, npages;
+	int flag = PTATTR_WRITABLE | PTATTR_ACTIVE;
+	void *v = (void *)fixed_virt;
+
+	poffset = phys & (PAGE_SIZE - 1);
+	paligned = phys & PAGE_MASK;
+	npages = (poffset + size + PAGE_SIZE - 1) >> PAGE_SHIFT;
+
+	if (uncachable) {
+		flag |= PTATTR_UNCACHABLE;
+	}
+
+	kprintf("map_fixed: %lx => %p (%d pages)\n", paligned, v, npages);
+
+	for (i = 0; i < npages; i++) {
+		__set_pt_page(init_pt, (void *)fixed_virt, paligned, flag);
+
+		fixed_virt += PAGE_SIZE;
+		paligned += PAGE_SIZE;
+	}
+	
+	flush_tlb();
+
+	return (char *)v + poffset;
+}
+
+void init_low_area(struct page_table *pt)
+{
+	set_pt_large_page(pt, 0, 0, PTATTR_WRITABLE);
+}
+
+void init_page_table(void)
+{
+	init_pt = arch_alloc_page(0);
+	
+	memset(init_pt, 0, sizeof(PAGE_SIZE));
+
+	/* Normal memory area */
+	init_normal_area(init_pt);
+	init_fixed_area(init_pt);
+	init_low_area(init_pt);
+	init_text_area(init_pt);
+
+	load_page_table(init_pt);
+	kprintf("Page table is now at %p\n", init_pt);
+}
+
+extern void __reserve_arch_pages(unsigned long, unsigned long,
+                                 void (*)(unsigned long, unsigned long, int));
+
+void aal_mc_reserve_arch_pages(unsigned long start, unsigned long end,
+                               void (*cb)(unsigned long, unsigned long, int))
+{
+	/* Reserve Text + temporal heap */
+	cb(virt_to_phys(_head), virt_to_phys(get_last_early_heap()), 0);
+	/* Reserve trampoline area to boot the second ap */
+	cb(AP_TRAMPOLINE, AP_TRAMPOLINE + AP_TRAMPOLINE_SIZE, 0);
+	/* Reserve the null page */
+	cb(0, PAGE_SIZE, 0);
+	/* Micro-arch specific */
+	__reserve_arch_pages(start, end, cb);
+}
+
+void aal_mc_set_page_allocator(struct aal_mc_pa_ops *ops)
+{
+	last_page = NULL;
+	pa_ops = ops;
+}
+
+unsigned long virt_to_phys(void *v)
+{
+	unsigned long va = (unsigned long)v;
+	
+	if (va >= MAP_KERNEL_START) {
+		return va - MAP_KERNEL_START + x86_kernel_phys_base;
+	} else {
+		return va - MAP_ST_START;
+	}
+}
+void *phys_to_virt(unsigned long p)
+{
+	return (void *)(p + MAP_ST_START);
+}
--- a/arch/x86/kernel/mikc.c
+++ b/arch/x86/kernel/mikc.c
@@ -0,0 +1,36 @@
+#include <aal/ikc.h>
+#include <aal/lock.h>
+#include <ikc/msg.h>
+#include <memory.h>
+#include <string.h>
+
+extern void arch_set_mikc_queue(void *r, void *w);
+aal_ikc_ph_t arch_master_channel_packet_handler;
+
+int aal_mc_ikc_init_first_local(struct aal_ikc_channel_desc *channel,
+                                aal_ikc_ph_t packet_handler)
+{
+	struct aal_ikc_queue_head *rq, *wq;
+
+	aal_ikc_system_init(NULL);
+
+	memset(channel, 0, sizeof(struct aal_ikc_channel_desc));
+
+	/* Place both sides in this side */
+	rq = arch_alloc_page(0);
+	wq = arch_alloc_page(0);
+
+	aal_ikc_init_queue(rq, 0, 0, PAGE_SIZE, MASTER_IKCQ_PKTSIZE);
+	aal_ikc_init_queue(wq, 0, 0, PAGE_SIZE, MASTER_IKCQ_PKTSIZE);
+
+	arch_master_channel_packet_handler = packet_handler;
+
+	aal_ikc_init_desc(channel, IKC_OS_HOST, 0, rq, wq,
+	                  aal_ikc_master_channel_packet_handler);
+	aal_ikc_enable_channel(channel);
+
+	/* Set boot parameter */
+	arch_set_mikc_queue(rq, wq);
+
+	return 0;
+}
--- a/arch/x86/kernel/perfctr.c
+++ b/arch/x86/kernel/perfctr.c
@@ -0,0 +1,129 @@
+#include <aal/perfctr.h>
+#include <march.h>
+#include <errno.h>
+#include <aal/debug.h>
+#include <registers.h>
+
+extern unsigned int *x86_march_perfmap;
+
+#define X86_CR4_PCE     0x00000100
+
+void x86_init_perfctr(void)
+{
+	unsigned long reg;
+
+	/* Allow PMC to be read from user space */
+	asm volatile("movq %%cr4, %0" : "=r"(reg));
+	reg |= X86_CR4_PCE;
+	asm volatile("movq %0, %%cr4" : : "r"(reg));
+}
+
+static int set_perfctr_x86_direct(int counter, int mode, unsigned int value)
+{
+	if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
+		return -EINVAL;
+	}
+
+	if (mode & PERFCTR_USER_MODE) {
+		value |= 1 << 16;
+	}
+	if (mode & PERFCTR_KERNEL_MODE) {
+		value |= 1 << 17;
+	}
+    //	wrmsr(MSR_PERF_GLOBAL_CTRL, 0);
+
+	value |= (1 << 22) | (1 << 18); /* EN */
+
+	wrmsr(MSR_IA32_PERFEVTSEL0 + counter, value);
+
+	kprintf("wrmsr: %d <= %x\n", MSR_PERF_GLOBAL_CTRL, 0);
+	kprintf("wrmsr: %d <= %x\n", MSR_IA32_PERFEVTSEL0 + counter, value);
+	return 0;
+}
+
+static int set_perfctr_x86(int counter, int event, int mask, int inv, int count,
+                           int mode)
+{
+	return set_perfctr_x86_direct(counter, mode,
+	                              CVAL2(event, mask, inv, count));
+}
+
+int aal_mc_perfctr_init(int counter, enum aal_perfctr_type type, int mode)
+{
+	if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
+		return -EINVAL;
+	}
+	if (type < 0 || type >= PERFCTR_MAX_TYPE) {
+		return -EINVAL;
+	}
+	if (!x86_march_perfmap[type]) {
+		return -EINVAL;
+	}
+
+	return set_perfctr_x86_direct(counter, mode, x86_march_perfmap[type]);
+}
+
+#ifdef HAVE_MARCH_PERFCTR_START
+extern void x86_march_perfctr_start(unsigned long counter_mask);
+#endif
+
+int aal_mc_perfctr_start(unsigned long counter_mask)
+{
+	unsigned int value = 0;
+
+#ifdef HAVE_MARCH_PERFCTR_START
+	x86_march_perfctr_start(counter_mask);
+#endif
+	counter_mask &= ((1 << X86_IA32_NUM_PERF_COUNTERS) - 1);
+	value = rdmsr(MSR_PERF_GLOBAL_CTRL);
+    value |= counter_mask;
+	wrmsr(MSR_PERF_GLOBAL_CTRL, value);
+
+	return 0;
+}
+
+int aal_mc_perfctr_stop(unsigned long counter_mask)
+{
+	unsigned int value;
+
+	counter_mask &= ((1 << X86_IA32_NUM_PERF_COUNTERS) - 1);
+	value = rdmsr(MSR_PERF_GLOBAL_CTRL);
+	value &= ~counter_mask;
+	wrmsr(MSR_PERF_GLOBAL_CTRL, value);
+
+	return 0;
+}
+
+int aal_mc_perfctr_reset(int counter)
+{
+	if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
+		return -EINVAL;
+	}
+
+	wrmsr(MSR_IA32_PMC0 + counter, 0);
+
+	return 0;
+}
+
+int aal_mc_perfctr_read_mask(unsigned long counter_mask, unsigned long *value)
+{
+	int i, j;
+
+	for (i = 0, j = 0; i < X86_IA32_NUM_PERF_COUNTERS && counter_mask;
+	     i++, counter_mask >>= 1) {
+		if (counter_mask & 1) {
+			value[j++] = rdpmc(i);
+		}
+	}
+	return 0;
+}
+
+unsigned long aal_mc_perfctr_read(int counter)
+{
+	if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
+		return -EINVAL;
+	}
+
+	return rdpmc(counter);
+}
+
--- a/arch/x86/kernel/trampoline.S
+++ b/arch/x86/kernel/trampoline.S
@@ -0,0 +1,150 @@
+#define BOOT_CS       0x10
+#define BOOT_DS       0x18
+#define BOOT_CS64     0x20
+
+#define MSR_EFER                0xc0000080
+#define EFER_LME                (1 << 8)
+	
+.section .rodata, "a", @progbits
+.code16
+
+.globl trampoline_code_data
+base = .
+trampoline_code_data:
+	jmp     cpu_start_body
+
+	.org	8
+header_pgtbl:
+	.quad	0		/* page table address */
+func_address:	
+	.quad	0		/* load address */
+arg:	
+	.quad	0		/* next address */
+stack_ptr:
+	.quad	0		/* initial stack */
+debug:
+	.quad	0		/* debug area */
+transit_pgtbl:
+	.quad	0		/* 32->64 bit table address */
+		
+cpu_start_body:
+	cli
+	wbinvd
+
+	movw	%cs, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+
+	xorl	%ebx, %ebx
+	movw	%cs, %bx
+	shll	$4, %ebx
+
+	movw	$0x29, debug - base
+
+	/* Adjust GDT ptr to the 32-bit physical address */
+	addl	%ebx, boot_gdtptr + 2 - base
+	addl    %ebx, 2f - base
+	addl    %ebx, start_64_vec - base
+	
+	lgdtl	boot_gdtptr - base
+	lidtl	boot_idtptr - base
+
+	jmp     1f
+1:	
+	
+	movl	%cr0, %edx
+	orb	$1, %dl
+	movl	%edx, %cr0
+
+	ljmpl	*(2f - base)
+2:	.long	protect_start - base
+	.word	BOOT_CS
+
+.balign  8
+.code32
+protect_start:
+	movl    $(BOOT_DS), %eax
+	movl	%eax, %ds
+	movl    %eax, %ss
+
+	/* Enable PAE */
+	movl    %cr4, %eax
+	orl     $0x20, %eax
+	movl    %eax, %cr4
+
+	leal    (stack_end - base)(%ebx), %esp
+	
+	/* Load a page table */
+	movl    (transit_pgtbl - base)(%ebx), %eax
+	movl	%eax, %cr3
+	
+1:
+
+	/* Enable Long Mode */
+	movl    $MSR_EFER, %ecx
+	movl 	$EFER_LME, %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Enable Paging */
+	movl	%cr0, %edx
+	orl	$0x80000000, %edx
+	movl	%edx, %cr0
+
+	ljmp    *(start_64_vec - base)(%ebx)
+	
+.code64
+.balign 8 
+start_64:
+	/* Okay, we are completely in the long mode ! */
+	/* So, use the real page table! */
+	movq	(header_pgtbl - base)(%ebx), %rax
+	movq	%rax, %cr3
+
+	movq    (func_address - base)(%ebx), %rcx
+	cmpq	$0, %rcx
+	/* If Loading IP is zero, just enter the infinite loop */
+	jz	3f
+
+	movq	(stack_ptr - base)(%ebx), %rax
+	cmpq	$0, %rax
+	jz	1f
+	movq	%rax, %rsp
+1:
+	/* Now, we prepare the parameters */
+	movq	(arg - base)(%ebx), %rdi
+	jmp	*%rcx
+
+3:	
+	cli
+	hlt
+	jmp	3b
+
+boot_idtptr:
+	.short	0
+	.long	0
+	
+boot_gdtptr:
+	.short	boot_gdt32_end - boot_gdt32
+	.long	boot_gdt32 - base
+	.align	4
+boot_gdt32:
+	.quad	0
+	.quad	0
+	.quad	0x00cf9b000000ffff
+	.quad	0x00cf93000000ffff
+	.quad   0x00af9b000000ffff
+	.quad	0x0000890000000067
+boot_gdt32_end:
+
+start_64_vec:
+	.long   start_64 - base
+	.word   BOOT_CS64, 0
+	
+stack:
+	.org    0x1000
+stack_end:
+.globl trampoline_code_data_end
+trampoline_code_data_end:
+