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support PERF_TYPE_{HARDWARE|HW_CACHE} in perf_event_open

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refs #829
This commit is contained in:
Ken Sato
2017-10-12 16:51:47 +09:00
parent 2ae6883a8b
commit 12840601e1
15 changed files with 685 additions and 51 deletions
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9
lib/include/ihk/cpu.h
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@@ -77,6 +77,15 @@ void ihk_mc_init_context(ihk_mc_kernel_context_t *new_ctx,
void *stack_pointer,
void (*next_function)(void));
int ihk_mc_get_extra_reg_id(unsigned long hw_config, unsigned long hw_config_ext);
unsigned int ihk_mc_get_nr_extra_regs();
int ihk_mc_get_extra_reg_idx(int id);
unsigned int ihk_mc_get_extra_reg_msr(int id);
unsigned long ihk_mc_get_extra_reg_event(int id);
unsigned long ihk_mc_hw_event_map(unsigned long hw_event);
unsigned long ihk_mc_hw_cache_event_map(unsigned long hw_cache_event);
unsigned long ihk_mc_hw_cache_extra_reg_map(unsigned long hw_cache_event);
/* returns the 'prev' argument of the call that caused the switch to the context returned. */
void *ihk_mc_switch_context(ihk_mc_kernel_context_t *old_ctx,
ihk_mc_kernel_context_t *new_ctx,

3
lib/include/ihk/perfctr.h
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@@ -18,6 +18,8 @@
#include <types.h>
#endif /*POSTK_DEBUG_TEMP_FIX_29*/
#include <mc_perf_event.h>
#define PERFCTR_USER_MODE 0x01
#define PERFCTR_KERNEL_MODE 0x02
@@ -60,6 +62,7 @@ int ihk_mc_perfctr_init_raw(int counter, uint64_t config, int mode);
int ihk_mc_perfctr_init(int counter, enum ihk_perfctr_type type, int mode);
int ihk_mc_perfctr_init_raw(int counter, unsigned int code, int mode);
#endif/*POSTK_DEBUG_TEMP_FIX_29*/
int ihk_mc_perfctr_set_extra(struct mc_perf_event *event);
#ifdef POSTK_DEBUG_TEMP_FIX_30
int ihk_mc_perfctr_start(int counter);
int ihk_mc_perfctr_stop(int counter);

48
lib/include/mc_perf_event.h
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@@ -2,9 +2,9 @@
#ifndef MC_PERF_EVENT_H
#define MC_PERF_EVENT_H
#ifdef POSTK_DEBUG_TEMP_FIX_32
//#ifdef POSTK_DEBUG_TEMP_FIX_32
#include <list.h>
#endif /*POSTK_DEBUG_TEMP_FIX_32*/
//#endif /*POSTK_DEBUG_TEMP_FIX_32*/
#include <march.h>
struct perf_event_attr;
@@ -105,6 +105,40 @@ enum perf_hw_id {
PERF_COUNT_HW_MAX, /* non-ABI */
};
/*
* Generalized hardware cache events:
*
* { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
* { read, write, prefetch } x
* { accesses, misses }
*/
enum perf_hw_cache_id {
PERF_COUNT_HW_CACHE_L1D = 0,
PERF_COUNT_HW_CACHE_L1I = 1,
PERF_COUNT_HW_CACHE_LL = 2,
PERF_COUNT_HW_CACHE_DTLB = 3,
PERF_COUNT_HW_CACHE_ITLB = 4,
PERF_COUNT_HW_CACHE_BPU = 5,
PERF_COUNT_HW_CACHE_NODE = 6,
PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
};
enum perf_hw_cache_op_id {
PERF_COUNT_HW_CACHE_OP_READ = 0,
PERF_COUNT_HW_CACHE_OP_WRITE = 1,
PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
};
enum perf_hw_cache_op_result_id {
PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
};
/*
* Hardware event_id to monitor via a performance monitoring event:
*/
@@ -218,8 +252,18 @@ struct perf_event_attr {
#endif
};
struct hw_perf_event_extra {
unsigned long config;
unsigned int reg;
int idx;
};
struct mc_perf_event {
struct perf_event_attr attr;
struct hw_perf_event_extra extra_reg;
unsigned long hw_config;
unsigned long hw_config_ext;
int cpu_id;
int counter_id; // counter_id
unsigned long count; // counter_value