362 lines
16 KiB
C++
362 lines
16 KiB
C++
#include <functional>
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#include <string>
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#include <type_traits>
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#include <vector>
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#include "ahbm.h"
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#include "apbp.h"
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#include "btdmp.h"
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#include "dma.h"
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#include "memory_interface.h"
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#include "mmio.h"
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#include "timer.h"
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namespace Teakra {
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auto NoSet(const std::string& debug_string) {
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return [debug_string](u16) { printf("Warning: NoSet on %s\n", debug_string.data()); };
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}
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auto NoGet(const std::string& debug_string) {
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return [debug_string]() -> u16 {
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printf("Warning: NoGet on %s\n", debug_string.data());
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return 0;
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};
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}
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struct BitFieldSlot {
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unsigned pos;
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unsigned length;
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std::function<void(u16)> set;
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std::function<u16(void)> get;
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template <typename T>
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static BitFieldSlot RefSlot(unsigned pos, unsigned length, T& var) {
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static_assert(
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std::is_same_v<u16,
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typename std::conditional_t<std::is_enum_v<T>, std::underlying_type<T>,
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std::enable_if<true, T>>::type>);
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BitFieldSlot slot{pos, length, {}, {}};
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slot.set = [&var](u16 value) { var = static_cast<T>(value); };
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slot.get = [&var]() -> u16 { return static_cast<u16>(var); };
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return slot;
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}
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};
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struct Cell {
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std::function<void(u16)> set;
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std::function<u16(void)> get;
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u16 index = 0;
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Cell(std::function<void(u16)> set, std::function<u16(void)> get)
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: set(std::move(set)), get(std::move(get)) {}
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Cell() {
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std::shared_ptr<u16> storage = std::make_shared<u16>(0);
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set = [storage, this](u16 value) {
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*storage = value;
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std::printf("MMIO: cell %04X set = %04X\n", index, value);
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};
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get = [storage, this]() -> u16 {
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std::printf("MMIO: cell %04X get\n", index);
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return *storage;
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};
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}
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static Cell ConstCell(u16 constant) {
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Cell cell({}, {});
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cell.set = NoSet("");
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cell.get = [constant]() -> u16 { return constant; };
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return cell;
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}
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static Cell RefCell(u16& var) {
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Cell cell({}, {});
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cell.set = [&var](u16 value) { var = value; };
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cell.get = [&var]() -> u16 { return var; };
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return cell;
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}
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static Cell MirrorCell(Cell* mirror) {
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Cell cell({}, {});
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cell.set = [mirror](u16 value) { mirror->set(value); };
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cell.get = [mirror]() -> u16 { return mirror->get(); };
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return cell;
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}
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static Cell BitFieldCell(const std::vector<BitFieldSlot>& slots) {
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Cell cell({}, {});
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std::shared_ptr<u16> storage = std::make_shared<u16>(0);
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cell.set = [storage, slots](u16 value) {
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for (const auto& slot : slots) {
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if (slot.set) {
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slot.set((value >> slot.pos) & ((1 << slot.length) - 1));
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}
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}
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*storage = value;
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};
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cell.get = [storage, slots]() -> u16 {
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u16 value = *storage;
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for (const auto& slot : slots) {
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if (slot.get) {
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value &= ~(((1 << slot.length) - 1) << slot.pos);
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value |= slot.get() << slot.pos;
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}
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}
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return value;
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};
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return cell;
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}
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};
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class MMIORegion::Impl {
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public:
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std::array<Cell, 0x800> cells{};
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Impl() {
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for (std::size_t i = 0; i < cells.size(); ++i) {
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cells[i].index = (u16)i;
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}
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}
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};
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MMIORegion::MMIORegion(MemoryInterfaceUnit& miu, ICU& icu, Apbp& apbp_from_cpu, Apbp& apbp_from_dsp,
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std::array<Timer, 2>& timer, Dma& dma, Ahbm& ahbm,
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std::array<Btdmp, 2>& btdmp)
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: impl(new Impl) {
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using namespace std::placeholders;
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impl->cells[0x01A] = Cell::ConstCell(0xC902); // chip detect
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// Timer
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for (unsigned i = 0; i < 2; ++i) {
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impl->cells[0x20 + i * 0x10] = Cell::BitFieldCell({
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// TIMERx_CFG
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BitFieldSlot::RefSlot(0, 2, timer[i].scale), // TS
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BitFieldSlot::RefSlot(2, 3, timer[i].count_mode), // CM
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BitFieldSlot{6, 1, {}, {}}, // TP
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BitFieldSlot{7, 1, {}, {}}, // CT
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BitFieldSlot::RefSlot(8, 1, timer[i].pause), // PC
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BitFieldSlot::RefSlot(9, 1, timer[i].update_mmio), // MU
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BitFieldSlot{10, 1,
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[&timer, i](u16 v) {
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if (v)
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timer[i].Restart();
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},
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[]() -> u16 { return 0; }}, // RES
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BitFieldSlot{11, 1, {}, {}}, // BP
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BitFieldSlot{12, 1, {}, {}}, // CS
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BitFieldSlot{13, 1, {}, {}}, // GP
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BitFieldSlot{14, 2, {}, {}}, // TM
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});
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impl->cells[0x22 + i * 0x10].set = [&timer, i](u16 v) {
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if (v)
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timer[i].TickEvent();
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}; // TIMERx_EW
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impl->cells[0x22 + i * 0x10].get = []() -> u16 { return 0; };
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impl->cells[0x24 + i * 0x10] = Cell::RefCell(timer[i].start_low); // TIMERx_SCL
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impl->cells[0x26 + i * 0x10] = Cell::RefCell(timer[i].start_high); // TIMERx_SCH
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impl->cells[0x28 + i * 0x10] = Cell::RefCell(timer[i].counter_low); // TIMERx_CCL
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impl->cells[0x2A + i * 0x10] = Cell::RefCell(timer[i].counter_high); // TIMERx_CCH
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impl->cells[0x2C + i * 0x10] = Cell(); // TIMERx_SPWMCL
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impl->cells[0x2E + i * 0x10] = Cell(); // TIMERx_SPWMCH
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}
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// APBP
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for (unsigned i = 0; i < 3; ++i) {
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impl->cells[0x0C0 + i * 4].set = std::bind(&Apbp::SendData, &apbp_from_dsp, i, _1);
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impl->cells[0x0C0 + i * 4].get = std::bind(&Apbp::PeekData, &apbp_from_dsp, i);
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impl->cells[0x0C2 + i * 4].set = [](u16) {};
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impl->cells[0x0C2 + i * 4].get = std::bind(&Apbp::RecvData, &apbp_from_cpu, i);
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}
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impl->cells[0x0CC].set = std::bind(&Apbp::SetSemaphore, &apbp_from_dsp, _1);
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impl->cells[0x0CC].get = std::bind(&Apbp::GetSemaphore, &apbp_from_dsp);
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impl->cells[0x0CE].set = std::bind(&Apbp::MaskSemaphore, &apbp_from_cpu, _1);
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impl->cells[0x0CE].get = std::bind(&Apbp::GetSemaphoreMask, &apbp_from_cpu);
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impl->cells[0x0D0].set = std::bind(&Apbp::ClearSemaphore, &apbp_from_cpu, _1);
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impl->cells[0x0D0].get = []() -> u16 { return 0; };
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impl->cells[0x0D2].set = [](u16) {};
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impl->cells[0x0D2].get = std::bind(&Apbp::GetSemaphore, &apbp_from_cpu);
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impl->cells[0x0D4] = Cell::BitFieldCell({
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BitFieldSlot{2, 1, {}, {}}, // ARM side endianness flag
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BitFieldSlot{8, 1,
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[&apbp_from_cpu](u16 v) { return apbp_from_cpu.SetDisableInterrupt(0, v); },
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[&apbp_from_cpu]() -> u16 { return apbp_from_cpu.GetDisableInterrupt(0); }},
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BitFieldSlot{12, 1,
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[&apbp_from_cpu](u16 v) { return apbp_from_cpu.SetDisableInterrupt(1, v); },
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[&apbp_from_cpu]() -> u16 { return apbp_from_cpu.GetDisableInterrupt(1); }},
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BitFieldSlot{13, 1,
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[&apbp_from_cpu](u16 v) { return apbp_from_cpu.SetDisableInterrupt(2, v); },
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[&apbp_from_cpu]() -> u16 { return apbp_from_cpu.GetDisableInterrupt(2); }},
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});
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impl->cells[0x0D6] = Cell::BitFieldCell({
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BitFieldSlot{5, 1, {}, [&apbp_from_dsp]() -> u16 { return apbp_from_dsp.IsDataReady(0); }},
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BitFieldSlot{6, 1, {}, [&apbp_from_dsp]() -> u16 { return apbp_from_dsp.IsDataReady(1); }},
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BitFieldSlot{7, 1, {}, [&apbp_from_dsp]() -> u16 { return apbp_from_dsp.IsDataReady(2); }},
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BitFieldSlot{8, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsDataReady(0); }},
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BitFieldSlot{
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9, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsSemaphoreSignaled(); }},
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BitFieldSlot{12, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsDataReady(1); }},
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BitFieldSlot{13, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsDataReady(2); }},
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});
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// This register is a mirror of CPU side register DSP_PSTS
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impl->cells[0x0D8] = Cell::BitFieldCell({
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BitFieldSlot{
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9, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsSemaphoreSignaled(); }},
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BitFieldSlot{10, 1, {}, [&apbp_from_dsp]() -> u16 { return apbp_from_dsp.IsDataReady(0); }},
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BitFieldSlot{11, 1, {}, [&apbp_from_dsp]() -> u16 { return apbp_from_dsp.IsDataReady(1); }},
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BitFieldSlot{12, 1, {}, [&apbp_from_dsp]() -> u16 { return apbp_from_dsp.IsDataReady(2); }},
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BitFieldSlot{13, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsDataReady(0); }},
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BitFieldSlot{14, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsDataReady(1); }},
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BitFieldSlot{15, 1, {}, [&apbp_from_cpu]() -> u16 { return apbp_from_cpu.IsDataReady(2); }},
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});
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// AHBM
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impl->cells[0x0E0].set = NoSet("AHBM::BusyFlag");
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impl->cells[0x0E0].get = std::bind(&Ahbm::GetBusyFlag, &ahbm);
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for (u16 i = 0; i < 3; ++i) {
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impl->cells[0x0E2 + i * 6] = Cell::BitFieldCell({
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// BitFieldSlot{0, 1, ?, ?},
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BitFieldSlot{1, 2, std::bind(&Ahbm::SetBurstSize, &ahbm, i, _1),
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std::bind(&Ahbm::GetBurstSize, &ahbm, i)},
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BitFieldSlot{4, 2, std::bind(&Ahbm::SetUnitSize, &ahbm, i, _1),
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std::bind(&Ahbm::GetUnitSize, &ahbm, i)},
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});
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impl->cells[0x0E4 + i * 6] = Cell::BitFieldCell({
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BitFieldSlot{8, 1, std::bind(&Ahbm::SetDirection, &ahbm, i, _1),
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std::bind(&Ahbm::GetDirection, &ahbm, i)},
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// BitFieldSlot{9, 1, ?, ?},
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});
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impl->cells[0x0E6 + i * 6].set = std::bind(&Ahbm::SetDmaChannel, &ahbm, i, _1);
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impl->cells[0x0E6 + i * 6].get = std::bind(&Ahbm::GetDmaChannel, &ahbm, i);
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}
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// MIU
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// impl->cells[0x100]; // MIU_WSCFG0
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// impl->cells[0x102]; // MIU_WSCFG1
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// impl->cells[0x104]; // MIU_Z0WSCFG
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// impl->cells[0x106]; // MIU_Z1WSCFG
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// impl->cells[0x108]; // MIU_Z2WSCFG
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// impl->cells[0x10C]; // MIU_Z3WSCFG
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impl->cells[0x10E] = Cell::RefCell(miu.x_page); // MIU_XPAGE
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impl->cells[0x110] = Cell::RefCell(miu.y_page); // MIU_YPAGE
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impl->cells[0x112] = Cell::RefCell(miu.z_page); // MIU_ZPAGE
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impl->cells[0x114] = Cell::BitFieldCell({
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// MIU_PAGE0CFG
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BitFieldSlot::RefSlot(0, 6, miu.x_size[0]),
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BitFieldSlot::RefSlot(8, 6, miu.y_size[0]),
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});
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impl->cells[0x116] = Cell::BitFieldCell({
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// MIU_PAGE1CFG
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BitFieldSlot::RefSlot(0, 6, miu.x_size[1]),
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BitFieldSlot::RefSlot(8, 6, miu.y_size[1]),
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});
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// impl->cells[0x118]; // MIU_OFFPAGECFG
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impl->cells[0x11A] = Cell::BitFieldCell({
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BitFieldSlot{0, 1, {}, {}}, // PP
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BitFieldSlot{1, 1, {}, {}}, // TESTP
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BitFieldSlot{2, 1, {}, {}}, // INTP
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BitFieldSlot{4, 1, {}, {}}, // ZSINGLEP
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BitFieldSlot::RefSlot(6, 1, miu.page_mode), // PAGEMODE
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});
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// impl->cells[0x11C]; // MIU_DLCFG
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impl->cells[0x11E] = Cell::RefCell(miu.mmio_base); // MIU_MMIOBASE
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// impl->cells[0x120]; // MIU_OBSCFG
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// impl->cells[0x122]; // MIU_POLARITY
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// DMA
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impl->cells[0x184].set = std::bind(&Dma::EnableChannel, &dma, _1);
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impl->cells[0x184].get = std::bind(&Dma::GetChannelEnabled, &dma);
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impl->cells[0x18C].get = []() -> u16 { return 0xFFFF; }; // SEOX ?
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impl->cells[0x1BE].set = std::bind(&Dma::ActivateChannel, &dma, _1);
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impl->cells[0x1BE].get = std::bind(&Dma::GetActiveChannel, &dma);
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impl->cells[0x1C0].set = std::bind(&Dma::SetAddrSrcLow, &dma, _1);
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impl->cells[0x1C0].get = std::bind(&Dma::GetAddrSrcLow, &dma);
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impl->cells[0x1C2].set = std::bind(&Dma::SetAddrSrcHigh, &dma, _1);
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impl->cells[0x1C2].get = std::bind(&Dma::GetAddrSrcHigh, &dma);
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impl->cells[0x1C4].set = std::bind(&Dma::SetAddrDstLow, &dma, _1);
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impl->cells[0x1C4].get = std::bind(&Dma::GetAddrDstLow, &dma);
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impl->cells[0x1C6].set = std::bind(&Dma::SetAddrDstHigh, &dma, _1);
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impl->cells[0x1C6].get = std::bind(&Dma::GetAddrDstHigh, &dma);
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impl->cells[0x1C8].set = std::bind(&Dma::SetSize0, &dma, _1);
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impl->cells[0x1C8].get = std::bind(&Dma::GetSize0, &dma);
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impl->cells[0x1CA].set = std::bind(&Dma::SetSize1, &dma, _1);
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impl->cells[0x1CA].get = std::bind(&Dma::GetSize1, &dma);
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impl->cells[0x1CC].set = std::bind(&Dma::SetSize2, &dma, _1);
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impl->cells[0x1CC].get = std::bind(&Dma::GetSize2, &dma);
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impl->cells[0x1CE].set = std::bind(&Dma::SetSrcStep0, &dma, _1);
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impl->cells[0x1CE].get = std::bind(&Dma::GetSrcStep0, &dma);
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impl->cells[0x1D0].set = std::bind(&Dma::SetDstStep0, &dma, _1);
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impl->cells[0x1D0].get = std::bind(&Dma::GetDstStep0, &dma);
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impl->cells[0x1D2].set = std::bind(&Dma::SetSrcStep1, &dma, _1);
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impl->cells[0x1D2].get = std::bind(&Dma::GetSrcStep1, &dma);
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impl->cells[0x1D4].set = std::bind(&Dma::SetDstStep1, &dma, _1);
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impl->cells[0x1D4].get = std::bind(&Dma::GetDstStep1, &dma);
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impl->cells[0x1D6].set = std::bind(&Dma::SetSrcStep2, &dma, _1);
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impl->cells[0x1D6].get = std::bind(&Dma::GetSrcStep2, &dma);
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impl->cells[0x1D8].set = std::bind(&Dma::SetDstStep2, &dma, _1);
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impl->cells[0x1D8].get = std::bind(&Dma::GetDstStep2, &dma);
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impl->cells[0x1DA] = Cell::BitFieldCell({
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BitFieldSlot{0, 4, std::bind(&Dma::SetSrcSpace, &dma, _1),
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std::bind(&Dma::GetSrcSpace, &dma)},
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BitFieldSlot{4, 4, std::bind(&Dma::SetDstSpace, &dma, _1),
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std::bind(&Dma::GetDstSpace, &dma)},
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// BitFieldSlot{9, 1, ?, ?},
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BitFieldSlot{10, 1, std::bind(&Dma::SetDwordMode, &dma, _1),
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std::bind(&Dma::GetDwordMode, &dma)},
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});
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impl->cells[0x1DC].set = std::bind(&Dma::SetY, &dma, _1);
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impl->cells[0x1DC].get = std::bind(&Dma::GetY, &dma);
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impl->cells[0x1DE].set = std::bind(&Dma::SetZ, &dma, _1);
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impl->cells[0x1DE].get = std::bind(&Dma::GetZ, &dma);
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// ICU
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impl->cells[0x200].set = NoSet("ICU::GetRequest");
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impl->cells[0x200].get = std::bind(&ICU::GetRequest, &icu);
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impl->cells[0x202].set = std::bind(&ICU::Acknowledge, &icu, _1);
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impl->cells[0x202].get = std::bind(&ICU::GetAcknowledge, &icu);
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impl->cells[0x204].set = std::bind(&ICU::Trigger, &icu, _1);
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impl->cells[0x204].get = std::bind(&ICU::GetTrigger, &icu);
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impl->cells[0x206].set = std::bind(&ICU::SetEnable, &icu, 0, _1);
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impl->cells[0x206].get = std::bind(&ICU::GetEnable, &icu, 0);
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impl->cells[0x208].set = std::bind(&ICU::SetEnable, &icu, 1, _1);
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impl->cells[0x208].get = std::bind(&ICU::GetEnable, &icu, 1);
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impl->cells[0x20A].set = std::bind(&ICU::SetEnable, &icu, 2, _1);
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impl->cells[0x20A].get = std::bind(&ICU::GetEnable, &icu, 2);
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impl->cells[0x20C].set = std::bind(&ICU::SetEnableVectored, &icu, _1);
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impl->cells[0x20C].get = std::bind(&ICU::GetEnableVectored, &icu);
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// impl->cells[0x20E]; // polarity for each interrupt?
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// impl->cells[0x210]; // source type for each interrupt?
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for (unsigned i = 0; i < 16; ++i) {
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impl->cells[0x212 + i * 4] = Cell::BitFieldCell({
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BitFieldSlot::RefSlot(0, 2, icu.vector_high[i]),
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BitFieldSlot::RefSlot(15, 1, icu.vector_context_switch[i]),
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});
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impl->cells[0x214 + i * 4] = Cell::RefCell(icu.vector_low[i]);
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}
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// BTDMP
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for (u16 i = 0; i < 2; ++i) {
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impl->cells[0x2A2 + i * 0x80].set = std::bind(&Btdmp::SetTransmitClockConfig, &btdmp[i], _1);
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impl->cells[0x2A2 + i * 0x80].get = std::bind(&Btdmp::GetTransmitClockConfig, &btdmp[i]);
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impl->cells[0x2BE + i * 0x80].set = std::bind(&Btdmp::SetTransmitEnable, &btdmp[i], _1);
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impl->cells[0x2BE + i * 0x80].get = std::bind(&Btdmp::GetTransmitEnable, &btdmp[i]);
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impl->cells[0x2C2 + i * 0x80] = Cell::BitFieldCell({
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BitFieldSlot{3, 1, {}, std::bind(&Btdmp::GetTransmitFull, &btdmp[i])},
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BitFieldSlot{4, 1, {}, std::bind(&Btdmp::GetTransmitEmpty, &btdmp[i])},
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});
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impl->cells[0x2C6 + i * 0x80].set = std::bind(&Btdmp::Send, &btdmp[i], _1);
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impl->cells[0x2CA + i * 0x80].set = std::bind(&Btdmp::SetTransmitFlush, &btdmp[i], _1);
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impl->cells[0x2CA + i * 0x80].get = std::bind(&Btdmp::GetTransmitFlush, &btdmp[i]);
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}
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}
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MMIORegion::~MMIORegion() = default;
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|
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u16 MMIORegion::Read(u16 addr) {
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u16 value = impl->cells[addr].get();
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return value;
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}
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void MMIORegion::Write(u16 addr, u16 value) {
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impl->cells[addr].set(value);
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}
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} // namespace Teakra
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