First Commit
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171
externals/teakra/hwtest/dsptester/firm/source
vendored
Normal file
171
externals/teakra/hwtest/dsptester/firm/source
vendored
Normal file
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segment p 0000
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br 0x0000$0800 always// reset vector
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br 0x0000$3000 always
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br 0x0000$3000 always
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br 0x0000$3000 always // int0
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data 0000
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data 0000
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data 0000
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data 0000
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data 0000
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data 0000
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br 0x0000$3000 always // int1
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data 0000
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data 0000
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data 0000
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data 0000
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data 0000
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data 0000
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br 0x0000$3000 always // int2
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segment p 0800 // pre-write shutdown sequence
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load 0x0080u8 page
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clr b0 always
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mov b0l [page:0x00c8u8] // T_REPLY2
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br 0x0000$1800 always // jump to epilogue first to dump the initial register value
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segment p 1000 // signal handler & prologue
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load 0x0000u8 page
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mov [page:0x0002u8] b0l
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brr 0x0003 eq
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clr b0 always
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mov b0l [page:0x0000u8]
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mov b0l [page:0x0002u8]
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mov [page:0x0001u8] b0l
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brr 0x0003 eq
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mov b0l [page:0x0000u8]
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clr b0 always
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mov b0l [page:0x0001u8]
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mov [page:0x0000u8] b0l
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br 0x0000$1000 eq
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mov 0x$2000 sp
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mov 0x$0003 mod0 // disable SAR and PS so a/b/p can be correctly loaded
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mov 0x$0000 mod3 // clear mod3 from E000 to 0000. Game does this at the beginning so let it be the default env
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pop r7
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pop r6
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pop r5
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pop r4
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pop r3
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pop r2
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pop r1
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pop r0
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pop a0l
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mov a0l mixp
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pop repc
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pop a0h
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mov a0h stepj0
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pop a0h
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mov a0h stepi0
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pop lc
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pop p1
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pop y1
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pop x1
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pop p0
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pop y0
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pop x0
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pop sv
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popa b1
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pop b1e
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popa b0
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pop b0e
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popa a1
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pop a1e
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popa a0
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pop a0e
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pop arp3
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pop arp2
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pop arp1
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pop arp0
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pop ar1
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pop ar0
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pop mod2
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pop mod1
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pop mod0
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pop stt2
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pop stt1
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pop stt0
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pop cfgj
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pop cfgi
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mov 0x$1000 sp
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br 0x0000$2000 always
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segment p 1800 // epilogue
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mov 0x$3000 sp
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push cfgi
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push cfgj
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push stt0
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push stt1
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push stt2
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push mod0
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push mod1
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push mod2
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push ar0
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push ar1
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push arp0
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push arp1
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push arp2
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push arp3
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mov 0x$0003 mod0 // disable SAR and PS so a/b/p can be correctly loaded
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push a0e
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pusha a0
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push a1e
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pusha a1
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push b0e
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pusha b0
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push b1e
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pusha b1
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push sv
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push x0
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push y0
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push p0
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push x1
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push y1
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push p1
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push lc
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mov stepi0 a0h
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push a0h
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mov stepj0 a0h
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push a0h
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push repc
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mov mixp a0l
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push a0l
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push r0
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push r1
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push r2
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push r3
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push r4
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push r5
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push r6
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push r7
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load 0x0000u8 page
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mov [page:0x0003u8] b0l
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brr 0x0003 eq
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clr b0 always
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mov b0l [page:0x0000u8]
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mov b0l [page:0x0003u8]
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br 0x0000$1000 always
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segment p 2000 // test area
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br 0x0000$1800 always
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segment p 3000 // interrupt
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reti always
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segment d 0000 // signal area
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data 0000
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data 0000
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data 0000
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data 0000
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