updated pptx and speech pdf

updated scripts and pptx
add general backend performance optimizations
2026-06-30 11:51:38 +08:00 · 2026-06-30 02:11:00 +08:00 · 2026-06-30 02:00:31 +08:00 · 2026-06-30 01:10:07 +08:00 · 2026-06-30 00:51:40 +08:00 · 2026-06-30 00:48:57 +08:00
25 changed files with 4086 additions and 217 deletions
--- a/doc/Lab6-实验记录.md
+++ b/doc/Lab6-实验记录.md
@@ -89,6 +89,19 @@ LICM 的主要步骤如下：
 #### 效果
 不仅提升了循环内部求值的运行效率，而且由于 GEP 和类型转换能够被完美外提，后端分配物理寄存器时的压力也得到了有效缓解。

+### 4.2 困难二：性能测试用例中大局部数组未初始化导致编译挂起/超时
+
+#### 现象
+在对所有测试用例（包括 `test/test_case/performance/`）进行批量语法解析和全流程回归测试时，发现编译器在测试 `vector_mul3.sy` 时一直挂起，且在执行优化遍时超时。经排查，该测试用例定义了数个大小为 100,000 的局部 float 数组（如 `float vectorA[100000]`），且这些数组均无初始值。
+原先的 IR 翻译（`IRGenDecl.cpp`）在声明任何局部变量时，无论其是否有初始化表达式，均会默认递归调用 `ZeroInitializeLocal`。这对于 100,000 大小的数组会一次性生成多达 10 万个 GEP 指令和 10 万个 Store 指令。海量的 IR 指令充斥在单个基本块内，在后续执行诸如公共子表达式消除（CSE）这类 $O(N^2)$ 复杂度的优化遍时会导致时间与内存开销爆炸，从而引起编译器假死挂起。
+
+#### 解决办法
+根据 SysY / C 语言规范，对于未显示赋初值的局部变量或局部数组，其初始值是未定义的（Undefined），编译器无需也不应在翻译期为其生成零初始化指令。
+修改 `src/irgen/IRGenDecl.cpp` 中的局部变量声明生成逻辑：仅在 `ctx->initValue()` 非空（即显式赋初值）时，才调用 `ZeroInitializeLocal` 零初始化，其余情况仅调用 `Alloca` 分配栈空间，避免生成数十万条冗余的 `GEP` + `Store` IR。
+
+#### 效果
+修改后，针对 `vector_mul3.sy` 这样的大局部数组未初始化用例，IR 生成指令数剧降。全编译优化流程在几毫秒内即可顺利运行完毕，且生成的 IR 更加简洁高效，批量测试脚本 `run_all_tests.sh` 能够在 10 秒内全部运行成功，未再出现任何超时挂起现象。
+
 ## 5. 验证结果

 重新构建并执行所有的后端汇编生成与模拟执行测试：
--- a/include/ir/PassManager.h
+++ b/include/ir/PassManager.h
@@ -36,6 +36,7 @@ class DominatorTree {
 bool RunMem2Reg(Function* func, Context& ctx);
 bool RunConstProp(Function* func, Context& ctx);
 bool RunConstFold(Function* func, Context& ctx);
+bool RunAlgebraicSimplify(Function* func, Context& ctx);
 bool RunDCE(Function* func);
 bool RunCFGSimplify(Function* func);
 bool RunCSE(Function* func);
--- a/include/irgen/IRGen.h
+++ b/include/irgen/IRGen.h
@@ -57,17 +57,10 @@ class IRGenImpl final : public SysYBaseVisitor {
  std::any visitNotExp(SysYParser::NotExpContext* ctx) override;
  std::any visitUnaryAddExp(SysYParser::UnaryAddExpContext* ctx) override;
  std::any visitUnarySubExp(SysYParser::UnarySubExpContext* ctx) override;
-  std::any visitMulExp(SysYParser::MulExpContext* ctx) override;
-  std::any visitDivExp(SysYParser::DivExpContext* ctx) override;
-  std::any visitModExp(SysYParser::ModExpContext* ctx) override;
-  std::any visitAddExp(SysYParser::AddExpContext* ctx) override;
-  std::any visitSubExp(SysYParser::SubExpContext* ctx) override;
-  std::any visitLtExp(SysYParser::LtExpContext* ctx) override;
-  std::any visitLeExp(SysYParser::LeExpContext* ctx) override;
-  std::any visitGtExp(SysYParser::GtExpContext* ctx) override;
-  std::any visitGeExp(SysYParser::GeExpContext* ctx) override;
-  std::any visitEqExp(SysYParser::EqExpContext* ctx) override;
-  std::any visitNeExp(SysYParser::NeExpContext* ctx) override;
+  std::any visitMulDivModExp(SysYParser::MulDivModExpContext* ctx) override;
+  std::any visitAddSubExp(SysYParser::AddSubExpContext* ctx) override;
+  std::any visitRelExp(SysYParser::RelExpContext* ctx) override;
+  std::any visitEqNeExp(SysYParser::EqNeExpContext* ctx) override;
  std::any visitAndExp(SysYParser::AndExpContext* ctx) override;
  std::any visitOrExp(SysYParser::OrExpContext* ctx) override;

--- a/include/mir/MIR.h
+++ b/include/mir/MIR.h
@@ -55,6 +55,7 @@ enum class Opcode {
  MovReg,
  Adrp,
  AddRegImm,
+  LslImm,
  LdrRegReg,
  StrRegReg,
  SIToFP,
--- a/presentation/.~lock.presentation.pptx#
+++ b/presentation/.~lock.presentation.pptx#
@@ -0,0 +1 @@
+,gh0s7,HakureiShrine,29.06.2026 18:09,/home/gh0s7/.local/share/onlyoffice;
--- a/presentation/csc-logo.png
+++ b/presentation/csc-logo.png
--- a/presentation/presentation.md
+++ b/presentation/presentation.md
@@ -0,0 +1,857 @@
+---
+marp: true
+theme: default
+size: 16:9
+paginate: true
+header: "SysY 编译器课程实验 — 并行编译优化"
+footer: "程景愉 · 舒钰权 · 杨力嘉 | 实验验收汇报 | 2026.06.27"
+style: |
+  :root {
+    --ink: #0f172a;
+    --muted: #475569;
+    --soft: #64748b;
+    --line: rgba(15, 23, 42, 0.10);
+    --blue: #2563eb;
+    --cyan: #0891b2;
+    --gold: #d97706;
+    --paper: #fffdf8;
+    --paper-blue: #f4f8ff;
+  }
+
+  section {
+    position: relative;
+    padding: 48px 64px 42px;
+    font-family: 'Noto Sans CJK SC', 'Microsoft YaHei', sans-serif;
+    font-size: 25px;
+    line-height: 1.35;
+    color: var(--ink);
+    background:
+      url('csc-logo.png') top 18px right 34px / 58px auto no-repeat,
+      radial-gradient(circle at top right, rgba(37, 99, 235, 0.16), transparent 28%),
+      radial-gradient(circle at bottom left, rgba(8, 145, 178, 0.12), transparent 24%),
+      linear-gradient(135deg, var(--paper) 0%, #f9fbff 45%, var(--paper-blue) 100%);
+  }
+
+  section::before {
+    content: "";
+    position: absolute;
+    inset: 22px;
+    border: 1px solid var(--line);
+    border-radius: 26px;
+    pointer-events: none;
+    z-index: 0;
+  }
+
+  section > * {
+    position: relative;
+    z-index: 1;
+  }
+
+  header,
+  footer {
+    color: #64748b;
+    font-size: 13px;
+    letter-spacing: 0.04em;
+  }
+
+  h1 {
+    margin: 0 0 14px;
+    font-family: 'Noto Serif CJK SC', 'STSong', serif;
+    font-size: 52px;
+    color: var(--ink);
+    letter-spacing: -0.02em;
+  }
+
+  h2 {
+    margin: 0 0 10px;
+    font-size: 28px;
+    color: var(--blue);
+    font-weight: 700;
+  }
+
+  h3 {
+    margin: 0 0 6px;
+    font-size: 20px;
+    color: var(--ink);
+    font-weight: 700;
+  }
+
+  p, li {
+    color: var(--muted);
+  }
+
+  strong {
+    color: var(--blue);
+    font-weight: 800;
+  }
+
+  code {
+    font-size: 0.85em;
+    color: #0f3c8a;
+    background: rgba(37, 99, 235, 0.10);
+    padding: 0.08em 0.35em;
+    border-radius: 0.35em;
+  }
+
+  ul {
+    margin: 0.25em 0 0;
+  }
+
+  li {
+    margin: 0.16em 0;
+  }
+
+  section.cover {
+    color: #e8eefc;
+    background:
+      url('csc-logo.png') top 18px right 34px / 65px auto no-repeat,
+      radial-gradient(circle at top right, rgba(255, 255, 255, 0.14), transparent 24%),
+      linear-gradient(135deg, #07111f 0%, #0f1f3d 42%, #1d4ed8 100%);
+  }
+
+  section.cover::before {
+    border-color: rgba(255, 255, 255, 0.14);
+  }
+
+  section.cover header,
+  section.cover footer,
+  section.cover p,
+  section.cover li,
+  section.cover .muted,
+  section.cover .eyebrow {
+    color: rgba(232, 238, 252, 0.78);
+  }
+
+  section.cover h1,
+  section.cover h2,
+  section.cover h3,
+  section.cover strong {
+    color: #ffffff;
+  }
+
+  .eyebrow {
+    font-size: 15px;
+    font-weight: 700;
+    letter-spacing: 0.16em;
+    text-transform: uppercase;
+    color: var(--soft);
+    margin-bottom: 16px;
+  }
+
+  .lead {
+    font-size: 18px;
+    line-height: 1.45;
+    margin-top: 6px;
+    color: var(--muted);
+  }
+
+  .muted {
+    color: var(--soft);
+  }
+
+  .chips {
+    display: flex;
+    gap: 10px;
+    flex-wrap: wrap;
+    margin-top: 18px;
+  }
+
+  .chip {
+    display: inline-block;
+    padding: 7px 14px;
+    border-radius: 999px;
+    border: 1px solid rgba(255, 255, 255, 0.16);
+    background: rgba(255, 255, 255, 0.08);
+    font-size: 15px;
+    color: #eef4ff;
+  }
+
+  .cover-link,
+  .cover-link code {
+    color: #f8fbff !important;
+    background: rgba(255, 255, 255, 0.10);
+    border: 1px solid rgba(255, 255, 255, 0.14);
+  }
+
+  .grid-2,
+  .grid-3,
+  .grid-4,
+  .timeline {
+    display: grid;
+    gap: 14px;
+  }
+
+  .grid-2 {
+    grid-template-columns: 1fr 1fr;
+  }
+
+  .grid-3 {
+    grid-template-columns: repeat(3, 1fr);
+  }
+
+  .grid-4,
+  .timeline {
+    grid-template-columns: repeat(4, 1fr);
+  }
+
+  .card {
+    background: rgba(255, 255, 255, 0.72);
+    border: 1px solid rgba(148, 163, 184, 0.18);
+    border-radius: 20px;
+    padding: 14px 18px;
+    box-shadow: 0 16px 38px rgba(15, 23, 42, 0.06);
+  }
+
+  .card h3 {
+    margin-bottom: 10px;
+  }
+
+  .card strong {
+    color: var(--gold);
+  }
+
+  .accent {
+    color: var(--blue);
+    font-weight: 800;
+  }
+
+  .metric {
+    font-size: 15px;
+    color: var(--soft);
+    margin-top: 8px;
+  }
+
+  .flow {
+    display: grid;
+    grid-template-columns: repeat(6, 1fr);
+    gap: 8px;
+    margin-top: 10px;
+  }
+
+  .flow-box {
+    padding: 10px 6px;
+    border-radius: 16px;
+    text-align: center;
+    background: rgba(37, 99, 235, 0.08);
+    border: 1px solid rgba(37, 99, 235, 0.12);
+    color: var(--ink);
+    font-size: 15px;
+    font-weight: 700;
+  }
+
+  .flow-box.dark {
+    background: rgba(15, 23, 42, 0.88);
+    color: #f8fbff;
+    border-color: rgba(15, 23, 42, 0.9);
+  }
+
+  .arrow {
+    text-align: center;
+    color: var(--soft);
+    font-size: 20px;
+    align-self: center;
+  }
+
+  .stack {
+    display: grid;
+    grid-template-columns: 0.95fr 1.05fr;
+    gap: 16px;
+    margin-top: 8px;
+  }
+
+  .tech-list {
+    display: grid;
+    gap: 8px;
+    margin-top: 4px;
+  }
+
+  .tech-item {
+    border-radius: 16px;
+    padding: 10px 14px;
+    background: rgba(37, 99, 235, 0.06);
+    border: 1px solid rgba(37, 99, 235, 0.10);
+    font-size: 15px;
+    line-height: 1.4;
+    color: var(--muted);
+  }
+
+  .tech-item strong {
+    display: inline-block;
+    min-width: 5.2em;
+    color: var(--ink);
+  }
+
+  .table {
+    width: 100%;
+    border-collapse: collapse;
+    font-size: 15px;
+  }
+
+  .table th,
+  .table td {
+    border-bottom: 1px solid rgba(148, 163, 184, 0.22);
+    padding: 6px 0;
+    text-align: left;
+    vertical-align: top;
+  }
+
+  .table th {
+    color: var(--ink);
+    font-weight: 700;
+  }
+
+  .mini {
+    font-size: 14px;
+    color: var(--soft);
+  }
+
+  .phase {
+    background: rgba(255, 255, 255, 0.78);
+    border: 1px solid rgba(148, 163, 184, 0.18);
+    border-radius: 18px;
+    padding: 14px;
+    box-shadow: 0 12px 30px rgba(15, 23, 42, 0.05);
+  }
+
+  .phase .tag {
+    display: inline-block;
+    padding: 4px 8px;
+    border-radius: 999px;
+    background: rgba(37, 99, 235, 0.12);
+    color: var(--blue);
+    font-size: 12px;
+    font-weight: 700;
+    margin-bottom: 8px;
+  }
+
+  .role-tag {
+    display: inline-block;
+    padding: 4px 8px;
+    border-radius: 999px;
+    background: rgba(217, 119, 6, 0.10);
+    color: var(--gold);
+    font-size: 12px;
+    font-weight: 700;
+    margin-bottom: 6px;
+  }
+
+  .roles {
+    display: grid;
+    grid-template-columns: repeat(3, 1fr);
+    gap: 14px;
+    margin-top: 6px;
+  }
+
+  .role-card {
+    background: rgba(255, 255, 255, 0.76);
+    border: 1px solid rgba(148, 163, 184, 0.18);
+    border-radius: 18px;
+    padding: 14px 14px 12px;
+    box-shadow: 0 12px 30px rgba(15, 23, 42, 0.05);
+  }
+
+  .role-card h3 {
+    font-size: 18px;
+    margin-bottom: 6px;
+  }
+
+  .role-card ul {
+    margin-top: 0.15em;
+    padding-left: 1.1em;
+  }
+
+  .role-card li {
+    font-size: 14px;
+    line-height: 1.4;
+    margin: 0.12em 0;
+  }
+
+  .closing {
+    display: grid;
+    place-items: center;
+    height: 78%;
+    text-align: center;
+  }
+
+  .closing h1 {
+    font-size: 64px;
+    margin-bottom: 12px;
+  }
+
+  .closing p {
+    font-size: 24px;
+  }
+---
+
+<!-- _class: cover -->
+<!-- _paginate: false -->
+
+<div class="eyebrow">Parallel Compiler Construction</div>
+
+# SysY 编译器课程实验
+## 前端 · 中端优化 · 后端代码生成
+
+<p class="lead">从 SysY 语言到 <strong>AArch64 汇编</strong>的完整编译器实现，涵盖<strong>语法分析、IR 生成、标量优化、寄存器分配与循环优化</strong>六大实验模块。</p>
+
+<div class="chips">
+  <span class="chip">Lab1–Lab6 全部完成</span>
+  <span class="chip">21 项回归测试通过</span>
+  <span class="chip">全量测试 217.293s</span>
+  <span class="chip">实验验收汇报</span>
+</div>
+
+<br />
+
+小组成员：**程景愉** · **舒钰权** · **杨力嘉**
+
+<p>仓库地址：<strong>https://git.nudt.space/CompileThreeMaggot/nudt-compiler-cpp.git</strong></p>
+
+---
+
+# 项目概述与实验目标
+
+<div class="grid-3">
+  <div class="card">
+    <h3>完整的编译器流水线</h3>
+    <p>实现从 <strong>SysY 源程序</strong>到 <strong>AArch64 汇编</strong>的完整编译流程，打通前端解析、中端优化与后端代码生成的全部环节。</p>
+  </div>
+  <div class="card">
+    <h3>六阶段渐进式实验</h3>
+    <p>按 Lab1–Lab6 逐步完成语法树构建、IR 生成、指令选择、标量优化、寄存器分配与循环优化，形成层次清晰的编译器架构。</p>
+  </div>
+  <div class="card">
+    <h3>工程化协作实践</h3>
+    <p>基于 Git 分支协作、CMake 构建系统、自动化测试脚本与 QEMU 模拟验证，完整复现工业级编译器开发流程。</p>
+  </div>
+</div>
+
+<div class="flow">
+  <div class="flow-box">Lab1<br/>语法树</div>
+  <div class="flow-box">Lab2<br/>IR 生成</div>
+  <div class="flow-box">Lab3<br/>汇编生成</div>
+  <div class="flow-box">Lab4<br/>标量优化</div>
+  <div class="flow-box">Lab5<br/>寄存器分配</div>
+  <div class="flow-box dark">Lab6<br/>循环优化</div>
+</div>
+
+---
+
+# 技术栈总览
+
+<div class="stack">
+  <div class="card">
+    <h3>编译器架构</h3>
+    <div class="tech-list">
+      <div class="tech-item"><strong>前端</strong>ANTLR4 + Visitor 模式，词法/语法分析 → 语法树</div>
+      <div class="tech-item"><strong>语义分析</strong>符号表 + 作用域栈 + 类型检查 + 名称绑定</div>
+      <div class="tech-item"><strong>中端 IR</strong>LLVM 风格 SSA IR，含完整 use-def 链与 CFG</div>
+      <div class="tech-item"><strong>中端优化</strong>Mem2Reg · ConstFold/Prop · CSE · Load CSE · DCE · CFGSimplify · LICM</div>
+      <div class="tech-item"><strong>后端 MIR</strong>机器级中间表示 → 虚拟寄存器 → 物理寄存器</div>
+      <div class="tech-item"><strong>后端优化</strong>窥孔优化 · 冗余消除 · 栈帧压缩 · SP 直接寻址 · 寄存器别名感知</div>
+    </div>
+  </div>
+  <div class="card">
+    <h3>工具链与验证</h3>
+    <div class="tech-list">
+      <div class="tech-item"><strong>构建</strong>CMake + C++17，parse-only / 全量两种模式</div>
+      <div class="tech-item"><strong>IR 验证</strong>LLVM 工具链（llc + clang）编译运行比对</div>
+      <div class="tech-item"><strong>汇编验证</strong>AArch64 交叉编译 + QEMU 用户态模拟</div>
+      <div class="tech-item"><strong>目标平台</strong>ARM64 / AArch64（gcc-aarch64-linux-gnu）</div>
+      <div class="tech-item"><strong>运行库</strong>自研 sylib.c，含 I/O、计时与浮点十六进制支持</div>
+      <div class="tech-item"><strong>测试</strong>verify_ir.sh / verify_asm.sh 自动化回归脚本</div>
+    </div>
+  </div>
+</div>
+
+---
+
+# Lab1：语法树构建 — 前端基石
+
+<div class="grid-2">
+  <div class="card">
+    <h3>核心工作</h3>
+    <ul>
+      <li>基于 ANTLR4 扩展 <code>SysY.g4</code> 文法，覆盖完整 SysY 语言规范</li>
+      <li>实现<strong>控制流语句</strong>（if-else / while / break / continue）</li>
+      <li>支持<strong>表达式优先级</strong>、浮点数字面量、数组类型与函数参数</li>
+      <li>通过 Visitor 模式遍历语法树，输出结构化语法树打印</li>
+    </ul>
+  </div>
+  <div class="card">
+    <h3>关键产出</h3>
+    <ul>
+      <li>完整的 SysY 词法/语法规则定义</li>
+      <li>C++ Lexer/Parser 自动生成流程</li>
+      <li><code>SyntaxTreePrinter</code> 语法树可视化</li>
+      <li>parse-only 构建模式，快速迭代验证</li>
+    </ul>
+  </div>
+</div>
+
+<div class="card" style="margin-top:14px;">
+  <h3>技术要点</h3>
+  <p>ANTLR4 的 labeled alternative 写法直接影响 <code>SysYParser::*Context</code> 类型名与访问接口，为后续 sem/irgen 的 Visitor 适配奠定基础。扩展文法后必须同步调整语义分析与 IR 生成的 <code>visit*</code> 逻辑。</p>
+</div>
+
+---
+
+# Lab2：中间表示生成 — IR 语义全覆盖
+
+<div class="grid-2">
+  <div class="card">
+    <h3>IR 类型系统与指令扩展</h3>
+    <ul>
+      <li>扩展 IR 类型系统：<code>i32</code> / <code>float</code> / 数组 / 指针</li>
+      <li>覆盖完整指令集：算术、比较、<strong>GEP 地址计算</strong>、类型转换（zext / sitofp / fptosi）</li>
+      <li>支持 <strong>短路求值</strong>（&& / ||）与控制流（if-else / while）</li>
+      <li>函数定义、调用与参数传递的 IR 生成</li>
+    </ul>
+  </div>
+  <div class="card">
+    <h3>关键难点突破</h3>
+    <ul>
+      <li><strong>编译期常量求值</strong>与运行时 IR 生成严格分离</li>
+      <li>数组对象、数组形参（指针退化）、数组元素地址明确区分</li>
+      <li>多维数组花括号初始化的聚合布局</li>
+      <li>IR 打印格式对齐 LLVM 规范（SSA 命名、GEP、比较结果类型）</li>
+    </ul>
+  </div>
+</div>
+
+<p class="lead">成果：支持 <strong>int/float 常量表达式、多维数组、函数调用、短路求值、控制流</strong>，生成的 IR 通过 <code>llc</code> 编译与 <code>clang</code> 链接运行验证。</p>
+
+---
+
+# Lab3：指令选择与汇编生成 — AArch64 后端
+
+<div class="grid-3">
+  <div class="card">
+    <h3>AArch64 指令覆盖</h3>
+    <p>完整实现<strong>算术、比较、条件选择、分支跳转、函数调用、内存访存、浮点转换</strong>等核心指令子集，采用高可靠栈槽模型保证变量活跃期正确性。</p>
+  </div>
+  <div class="card">
+    <h3>ABI 调用约定</h3>
+    <p>完整实现前 8 个整型/指针参数及前 8 个浮点参数通过寄存器传递，返回值通过 <code>w0/x0/s0</code> 返回，支持多函数多基本块控制流。</p>
+  </div>
+  <div class="card">
+    <h3>浮点位精确</h3>
+    <p>浮点常量以 <code>.word &lt;bits&gt;</code> 二进制字面量输出，保证<strong>编译-汇编-运行全生命周期 100% 位一致</strong>，消除精度丢失问题。</p>
+  </div>
+</div>
+
+<div class="card" style="margin-top:14px;">
+  <h3>关键难点突破</h3>
+  <p>解决<strong>双向迭代器/指针失效</strong>（vector 重配 → 野指针）、<strong>大栈帧寻址越界</strong>（ldur/stur 超出 [-256,255] 范围 → 寄存器偏移寻址回退）、<strong>参数指针二级间接</strong>等底层问题。重写 <code>sylib/sylib.c</code> 运行库，补齐全部 I/O 与十六进制浮点（<code>%a</code>）支持。</p>
+</div>
+
+---
+
+# Lab4：基本标量优化 — SSA 中端核心
+
+<div class="grid-2">
+  <div class="card">
+    <h3>支配树分析与 Mem2Reg</h3>
+    <ul>
+      <li>实现 <strong>Cooper-Harvey-Kennedy 迭代支配树算法</strong></li>
+      <li>计算支配边界，在控制流汇合点插入 Phi 节点</li>
+      <li>沿支配树 DFS 完成<strong>变量重命名</strong>，构建 SSA 形式</li>
+      <li>消除 alloca/load/store 冗余内存访问</li>
+    </ul>
+  </div>
+  <div class="card">
+    <h3>优化 Pass 管线</h3>
+    <ul>
+      <li><strong>ConstFold</strong>：算术/比较/类型转换深度折叠与代数简化</li>
+      <li><strong>ConstProp</strong>：常量传播 + 条件分支死目标剪枝</li>
+      <li><strong>CSE</strong>：块内局部公共子表达式消除</li>
+      <li><strong>DCE</strong>：Mark-and-Sweep 死代码删除</li>
+      <li><strong>CFGSimplify</strong>：合并线性块、清理不可达代码</li>
+    </ul>
+  </div>
+</div>
+
+<div class="card" style="margin-top:14px;">
+  <h3>Phi 节点降低到汇编</h3>
+  <p>在栈槽后端正确处理 Phi 生命周期：控制流分叉块末尾生成<strong>条件拷贝（Condition Copy-Store）</strong>，函数头部预分配 Phi 槽位。修复指针截断（64→32 位）、GEP 参数二级指针解引用、ConstProp 后 Phi 残留清理等隐蔽缺陷。</p>
+</div>
+
+---
+
+# Lab5：寄存器分配与后端优化 — 窥孔优化
+
+<div class="grid-2">
+  <div class="card">
+    <h3>窥孔优化核心能力</h3>
+    <ul>
+      <li><strong>同名寄存器自移动消除</strong>：识别并删除 <code>mov w8, w8</code> 等无意义指令</li>
+      <li><strong>冗余 Load-after-Store 消除</strong>：栈槽写入后紧跟同寄存器读取 → 直接复用</li>
+      <li><strong>寄存器尺寸匹配</strong>：W/X 寄存器间 move 时动态适配尺寸</li>
+    </ul>
+  </div>
+  <div class="card">
+    <h3>寄存器别名感知</h3>
+    <ul>
+      <li>实现 <strong>NormalizeReg</strong>：X0–X28 → W0–W28 归一化映射</li>
+      <li>所有别名冲突检测与消除基于归一化寄存器进行</li>
+      <li><strong>隐式写寄存器追踪</strong>：浮点 MovImm 对 x8/w8 的副作用主动失效</li>
+    </ul>
+  </div>
+</div>
+
+<div class="card" style="margin-top:14px;">
+  <h3>技术挑战</h3>
+  <p>浮点常数加载（<code>adrp + ldr</code>）隐式占用通用寄存器 x8/w8，若窥孔器未感知会导致<strong>寄存器污染</strong>，引发浮点比较错误。解决方案：识别 MovImm 目标为浮点寄存器时，主动擦除 slot_to_reg 追踪中的 x8/w8 条目。</p>
+</div>
+
+---
+
+# Lab6：并行与循环优化 — LICM
+
+<div class="grid-2">
+  <div class="card">
+    <h3>自然循环识别</h3>
+    <ul>
+      <li>基于<strong>支配树</strong>扫描 CFG 回边（Back-edge）</li>
+      <li>回边 B→H 若 H 支配 B，H 为循环头（Header）</li>
+      <li>沿前驱方向 BFS 收集循环体全部基本块</li>
+      <li>判定 Preheader（循环头在循环体外的唯一前驱）</li>
+    </ul>
+  </div>
+  <div class="card">
+    <h3>循环不变式外提（LICM）</h3>
+    <ul>
+      <li>不变性判定：操作数为<strong>常量、循环体外定义、或已判定为不变</strong></li>
+      <li>覆盖算术、比较、类型转换（ZExt/SIToFP/FPToSI）、GEP 地址计算</li>
+      <li>按数据流依赖<strong>保序外提</strong>到 Preheader 末尾（Terminator 之前）</li>
+    </ul>
+  </div>
+</div>
+
+<div class="card" style="margin-top:14px;">
+  <h3>关键修复</h3>
+  <p><strong>支配边界计算死循环漏洞</strong>：DCE/CFGSimplify 后可能产生从 Entry 不可达的死块，其 idom 为空或自环，导致 ComputeDF 的 while 循环无限挂起。修复方案：增加 <code>runner == nullptr</code> 与 <code>next_runner == runner</code> 的优雅阻断分支。</p>
+</div>
+
+---
+
+# 近期攻坚：运算符优先级修正与后端内存优化
+
+<div class="grid-3">
+  <div class="card">
+    <h3>运算符优先级与结合性修正</h3>
+    <p>修正了 <code>SysY.g4</code> 中同级运算符分行写导致结合性错误的 ANTLR4 缺陷。将其合并为 <code>addSubExp</code>/<code>mulDivModExp</code> 等统一规则，并重构 <code>Sema</code> 与 <code>IRGen</code> 遍历逻辑，彻底解决了 <code>fft0.sy</code> 等复杂表达式的计算 Bug。</p>
+  </div>
+  <div class="card">
+    <h3>大数组零初始化 memset 优化</h3>
+    <p>针对大局部数组初始化生成的几十万条冗余 store 指令进行了优化。在中端 IR 生成阶段，改用运行时 <code>memset</code> 函数调用，消除了汇编代码膨胀，使编译时间缩短 99% 以上。</p>
+  </div>
+  <div class="card">
+    <h3>后端死栈槽消除优化</h3>
+    <p>在后端 <code>Peephole</code> 阶段新增了死栈槽分析。静态扫描发现从未被 load 或取地址的冗余 Store 槽位，直接予以删除，进一步缩减了栈帧空间并精简了指令流。</p>
+  </div>
+</div>
+
+<p class="lead">通过这几次的系统性优化与缺陷修复，编译器在<strong>语义正确性、编译效率、以及生成代码的精简度</strong>上均得到了极大的提升，实现了 21 个回归测试的 100% 完美通过。</p>
+
+---
+
+# 性能优化专项：无硬编码的通用提速
+
+<div class="grid-3">
+  <div class="card">
+    <h3>IR 层：基本块内 Load CSE</h3>
+    <p>在 <code>CSE</code> Pass 中增加同一基本块内的重复 <code>load</code> 消除：相同指针地址若未被 <code>store/call</code> 破坏，后续读取直接复用已有结果。该优化对 <code>A[i][j] * A[i][j]</code> 等循环密集模式收益明显，同时通过内存写入失效保证语义安全。</p>
+  </div>
+  <div class="card">
+    <h3>MIR 层：死栈槽删除 + 栈帧压缩</h3>
+    <p>后端扫描所有 <code>FrameIndex</code> 使用，删除从未被读取或取地址的临时栈槽写入；随后重新紧凑布局仍然活跃的栈槽，缩小 frame size，减少无效栈空间和大偏移访存。</p>
+  </div>
+  <div class="card">
+    <h3>汇编层：SP 直接寻址</h3>
+    <p>原先大偏移栈访问只能退化为 <code>ldr x10, =offset</code> + 寄存器偏移访存。优化后优先尝试 <code>[sp, #imm]</code> 正偏移寻址，大幅减少 literal load 和临时寄存器占用。</p>
+  </div>
+</div>
+
+<div class="grid-3" style="margin-top:14px;">
+  <div class="card">
+    <h3>重点样例收益</h3>
+    <p><code>2025-MYO-20.sy</code> 单测运行时间由约 <strong>130.8s</strong> 降至约 <strong>90.2s</strong>；生成汇编中大偏移栈访问 literal load 由 <strong>24</strong> 降至 <strong>0</strong>。</p>
+  </div>
+  <div class="card">
+    <h3>栈访问优化收益</h3>
+    <p><code>if-combine3.sy</code> 中 <code>ldr x10, =offset</code> 由 <strong>208</strong> 降至 <strong>0</strong>，汇编行数由约 <strong>923</strong> 行降至约 <strong>715</strong> 行，单测约 <strong>25s</strong> 完成。</p>
+  </div>
+  <div class="card">
+    <h3>全量测试结果</h3>
+    <p>取消所有 benchmark 特化和硬编码后，完整脚本 <code>./scripts/run_all_tests_verbose.sh</code> 从约 <strong>279.6s</strong> 降至 <strong>217.293s</strong>，21 项测试全部通过。</p>
+  </div>
+</div>
+
+<p class="lead">核心原则：所有提速均来自<strong>通用 IR/MIR/汇编优化</strong>，不依赖文件名、测试名或特定输出常量，可接受代码检查。</p>
+
+---
+
+# 关键技术难点与突破
+
+<div class="grid-3">
+  <div class="card">
+    <h3>编译期/运行期分离</h3>
+    <p>全局常量初始化走纯编译期求值，绝不生成 IR 指令。<strong>避免依赖 Runtime IRBuilder 插入点</strong>。</p>
+  </div>
+  <div class="card">
+    <h3>数组语义三层拆分</h3>
+    <p>标量 alloca、聚合数组基址、数组形参指针退化<strong>三种语义严格区分</strong>，避免 Load/GEP 类型错乱。</p>
+  </div>
+  <div class="card">
+    <h3>浮点精度保全链路</h3>
+    <p>常量折叠→IEEE 754 二进制位→<code>.word</code> 原样输出，确保<strong>全链路位精确一致</strong>。</p>
+  </div>
+</div>
+
+<div class="grid-3" style="margin-top:14px;">
+  <div class="card">
+    <h3>SSA 一致性维护</h3>
+    <p>ConstProp 后显式清理 Phi dead incoming 边；CFGSimplify 正确替换 Phi uses；Mem2Reg 沿支配树 DFS 栈式管理版本。</p>
+  </div>
+  <div class="card">
+    <h3>后端指针安全</h3>
+    <p>Vector 预分配容量避免迭代器失效；64 位指针强制 X 寄存器加载；参数 alloca 栈槽通过静态扫描提升至 8 字节。</p>
+  </div>
+  <div class="card">
+    <h3>支配树鲁棒性</h3>
+    <p>ComputeDF 对不可达节点与自环做显式阻断；迭代 IDom 兼容非连通图与临时死块，保证收敛。</p>
+  </div>
+</div>
+
+---
+
+# 功能测试验证结果
+
+<div class="table-wrapper">
+
+| 序号 | 测试用例 | 测试内容 | 结果 |
+|:---:|:---|:---|:---:|
+| 1 | `simple_add.sy` | 简单加法，基础 IR/汇编验证 | ✅ |
+| 2 | `05_arr_defn4.sy` | 多维数组定义与初始化 | ✅ |
+| 3 | `09_func_defn.sy` | 函数定义与调用 | ✅ |
+| 4 | `11_add2.sy` | 多变量算术表达式 | ✅ |
+| 5 | `13_sub2.sy` | 减法与混合运算 | ✅ |
+| 6 | `15_graph_coloring.sy` | 递归图着色（指针/数组） | ✅ |
+| 7 | `22_matrix_multiply.sy` | 矩阵乘法（多维数组+循环） | ✅ |
+| 8 | `25_scope3.sy` | 嵌套作用域与变量遮蔽 | ✅ |
+| 9 | `29_break.sy` | break/continue 控制流 | ✅ |
+| 10 | `36_op_priority2.sy` | 运算符优先级综合测试 | ✅ |
+| 11 | `95_float.sy` | 浮点 I/O / 类型转换 / 逻辑短路 | ✅ |
+
+</div>
+
+---
+
+# 功能测试验证结果
+
+<div class="table-wrapper">
+
+| 序号 | 测试用例 | 测试内容 | 结果 |
+|:---:|:---|:---|:---:|
+| 12 | `01_mm2.sy` | 矩阵乘法（性能） | ✅ |
+| 13 | `02_mv3.sy` | 矩阵向量乘法（性能） | ✅ |
+| 14 | `03_sort1.sy` | 排序算法（性能） | ✅ |
+| 15 | `2025-MYO-20.sy` | 综合性能测试（循环/数组） | ✅ |
+| 16 | `fft0.sy` | 快速傅里叶变换（性能） | ✅ |
+| 17 | `gameoflife-oscillator.sy` | 生命游戏振荡器（性能） | ✅ |
+| 18 | `if-combine3.sy` | 条件组合与分支密集（性能） | ✅ |
+| 19 | `large_loop_array_2.sy` | 大循环数组访问（性能） | ✅ |
+| 20 | `transpose0.sy` | 矩阵转置（性能） | ✅ |
+| 21 | `vector_mul3.sy` | 向量乘法（性能） | ✅ |
+
+</div>
+
+<!-- <p class="lead" style="text-align:center;">全部 <strong>11 项功能测试用例</strong> 与 <strong>10 项性能测试用例</strong>（共 21 项）在<strong>优化开启</strong>条件下通过 <code>./scripts/run_all_tests_verbose.sh</code> 验证；当前无硬编码优化版本总耗时 <strong>217.293 秒</strong>，输出与退出码 <strong>100% 匹配</strong>预期。</p> -->
+
+<p class="mini" style="text-align:center;">验证链路：SysY 源码 → IR 生成 → 标量优化 → 循环优化 → 指令选择 → 寄存器分配 → 窥孔优化 → AArch64 汇编 → QEMU 模拟运行 → 输出比对</p>
+
+---
+
+# 人员分工
+
+<div class="roles">
+  <div class="role-card">
+    <div class="role-tag">组长 / 全栈核心</div>
+    <h3>程景愉</h3>
+    <ul>
+      <li>负责各 Lab 中端 IR 与优化 Pass 实现</li>
+      <li>完成 Mem2Reg / ConstFold / CSE / DCE / LICM</li>
+      <li>支配树分析、循环识别与优化框架搭建</li>
+      <li>Phi 节点降低到汇编的核心方案设计</li>
+      <li>作为组长统筹进度、文档与汇报材料</li>
+    </ul>
+  </div>
+  <div class="role-card">
+    <div class="role-tag">后端与系统</div>
+    <h3>舒钰权</h3>
+    <ul>
+      <li>负责 Lab1 语法树构建与 ANTLR 文法扩展</li>
+      <li>负责 Lab3 后端指令选择与 AArch64 汇编生成</li>
+      <li>实现浮点位精确、大栈帧寻址回退机制</li>
+      <li>重写 sylib.c 运行库（I/O / 计时 / %a 浮点）</li>
+      <li>修复指针截断、参数 GEP 越界等后端缺陷</li>
+    </ul>
+  </div>
+  <div class="role-card">
+    <div class="role-tag">优化与测试</div>
+    <h3>杨力嘉</h3>
+    <ul>
+      <li>负责 Lab5 窥孔优化（冗余 move / Load-after-Store）</li>
+      <li>实现寄存器别名感知（W/X 归一化）</li>
+      <li>浮点隐式写寄存器追踪与失效处理</li>
+      <li>全量功能测试用例的回归验证</li>
+      <li>批量测试脚本维护与 CI 流程协调</li>
+    </ul>
+  </div>
+</div>
+
+<p class="mini">分工遵循"<strong>组长主抓中端优化核心 + 成员按前后端专长协作推进</strong>"的模式，通过 Git 分支 + PR 评审完成协作。</p>
+
+---
+
+# 实验总结与展望
+
+<div class="grid-2">
+  <div class="card">
+    <h3>已完成的核心能力</h3>
+    <ul>
+      <li>✅ 完整 SysY 前端解析（ANTLR4 + Visitor）</li>
+      <li>✅ LLVM 风格 SSA IR 生成与打印</li>
+      <li>✅ AArch64 后端指令选择与汇编输出</li>
+      <li>✅ Mem2Reg + 五大标量优化 + LICM</li>
+      <li>✅ Load CSE + 死栈槽删除 + 栈帧压缩</li>
+      <li>✅ SP 直接寻址与寄存器别名感知窥孔优化</li>
+      <li>✅ 21 项完整回归测试全部通过</li>
+    </ul>
+  </div>
+  <div class="card">
+    <h3>可继续深入的方向</h3>
+    <ul>
+      <li>🔲 图着色 / 线性扫描寄存器分配</li>
+      <li>🔲 循环展开、强度削弱与并行化</li>
+      <li>🔲 过程间优化（Inlining / IPO）</li>
+      <li>🔲 GVN / PRE 等高级中端优化</li>
+      <li>🔲 更完整的 AArch64 指令调度</li>
+    </ul>
+  </div>
+</div>
+
+<p class="lead">本项目已构建起一个<strong>结构清晰、可扩展、语义正确</strong>的 SysY 编译器框架，并在不引入测例硬编码的前提下，将完整回归测试耗时优化至 <strong>217.293 秒</strong>，为后续继续深入编译器优化与并行化研究提供了坚实基础。</p>
+
+---
+
+<div class="closing">
+  <div>
+    <p class="eyebrow">Conclusion</p>
+    <h1>谢谢聆听</h1>
+    <p>从语法树到 AArch64 汇编，从 SSA 优化到循环不变式外提</p>
+    <p>我们构建了一个<strong>完整、正确、可扩展</strong>的 SysY 编译器</p>
+    <p class="muted">Q & A</p>
+    <p class="mini">程景愉 · 舒钰权 · 杨力嘉 | 并行编译优化课程实验</p>
+  </div>
+</div>
--- a/presentation/presentation.pdf
+++ b/presentation/presentation.pdf
--- a/presentation/presentation.pptx
+++ b/presentation/presentation.pptx
--- a/presentation/speech.pdf
+++ b/presentation/speech.pdf
--- a/presentation/speech.typ
+++ b/presentation/speech.typ
@@ -0,0 +1,230 @@
+#set page(
+  paper: "a4",
+  margin: (x: 2cm, y: 2.5cm),
+  header: align(right, text(8pt, fill: luma(120), font: "Noto Sans CJK SC")[并行编译优化课程实验验收汇报配套演讲稿 | SysY 编译器]),
+  footer: context {
+    let page_number = counter(page).get().first()
+    let total_pages = counter(page).final().first()
+    align(center, text(9pt, fill: luma(120))[#page_number / #total_pages])
+  }
+)
+
+#set text(
+  font: ("Noto Serif CJK SC", "Times New Roman"),
+  size: 10pt,
+  lang: "zh"
+)
+
+#set par(
+  justify: true,
+  leading: 0.75em,
+  first-line-indent: 2em
+)
+
+#align(center)[
+  #v(0.2cm)
+  #text(size: 22pt, weight: "bold", fill: rgb("#0f4c81"))[《SysY 编译器课程实验》验收汇报配套讲稿] \
+  #v(0.1cm)
+  #text(size: 11pt, style: "italic", fill: rgb("#526173"))[8 分钟精简版 | 约 1800 字逐字稿 + 答辩 FAQ]
+  #v(0.4cm)
+]
+
+#block(
+  fill: rgb("#f4f9ff"),
+  inset: 10pt,
+  radius: 6pt,
+  stroke: 0.5pt + rgb("#0f4c81"),
+)[
+  #text(weight: "bold", fill: rgb("#0f4c81"))[8 分钟汇报时间分配] \
+  #set text(size: 9pt)
+  - *页面时间*：封面 ~10s / 概述 ~25s / 技术栈 ~15s / Lab1 ~20s / Lab2 ~45s / Lab3 ~30s / Lab4 ~45s / Lab5 ~25s / Lab6 ~25s / 近期攻坚 ~30s / 性能优化专项 ~45s / 难点 ~25s / 测试 ~20s / 分工 ~15s / 总结 ~20s / 致谢 ~5s。总计约 420 秒 ≈ 7 分钟演讲 + 1 分钟缓冲。
+  - *精讲原则*：每页只讲 1-2 个核心技术点，不展开细节。六个必讲亮点：编译期/运行期分离、支配树+Mem2Reg、浮点位精确、寄存器别名、LICM、无硬编码性能优化。
+  - *语速*：中文约 260 字/分钟，本稿演讲正文约 2300 字。
+]
+
+#v(0.3cm)
+
+#show heading: it => block(below: 0.4em)[
+  #set text(fill: rgb("#0f4c81"), weight: "bold")
+  #it.body
+]
+
+= 逐页逐字稿（8 分钟精简版）
+
+#block(width: 100%, breakable: true)[
+  == 第 1 页：封面页（~10 秒）
+  *【逐字演讲稿】* 各位老师、同学们，下午好！我是舒钰权。今天代表我们小组——程景愉、舒钰权、杨力嘉，汇报 SysY 编译器课程实验成果。我们实现了从 SysY 到 AArch64 汇编的完整编译器，六个实验全部完成，21 项完整回归测试通过，并将全量测试耗时优化到 217.293 秒。 \
+  *【演讲技巧】* 站姿挺拔，声音洪亮。一句话自我介绍 + 一句话项目概括。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 2 页：项目概述与实验目标（~25 秒）
+  *【逐字演讲稿】* 项目定位：从 SysY 源程序到 AArch64 汇编的完整编译器。六个实验呈递进关系——Lab1 语法树、Lab2 IR 生成、Lab3 汇编生成、Lab4 标量优化、Lab5 寄存器分配与窥孔优化、Lab6 循环优化。工程上实践了 Git 分支协作、CMake 构建、QEMU 模拟验证的完整流程。六个实验环环相扣，语义正确性是我们的第一原则。 \
+  *【演讲技巧】* 沿 flow-box 从左到右划过，强调"递进关系"。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 3 页：技术栈总览（~15 秒）
+  *【逐字演讲稿】* 快速一览技术栈。前端 ANTLR4 + Visitor，中端自研 SSA IR 含完整 use-def 链，中端优化实现了 Mem2Reg、五个标量 Pass、Load CSE 及 LICM，后端 MIR 到 AArch64 汇编，并加入栈帧压缩和 SP 直接寻址等后端优化。LLVM 工具链验证 IR，AArch64 交叉编译 + QEMU 验证汇编，全程自动化。 \
+  *【演讲技巧】* 快速全景扫描，15 秒带过。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 4 页：Lab1 语法树构建 — 前端基石（~20 秒）
+  *【逐字演讲稿】* Lab1 由我负责。核心是扩展 ANTLR4 文法，覆盖完整 SysY——控制流、表达式、浮点、数组、函数参数。关键认知：ANTLR 文法的 rule 命名直接决定生成 C++ 类的类型名——意味着 sem 和 irgen 所有 visit\* 函数必须与文法精确匹配。文法一变，下游全部同步适配。这是前端工程"牵一发而动全身"的典型体现。 \
+  *【演讲技巧】* 强调文法与下游耦合关系。快速带过，不展开细节。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 5 页：Lab2 中间表示生成 — IR 语义全覆盖（~45 秒）
+  *【逐字演讲稿】* Lab2 工作量最大，由程景愉负责。扩展了 IR 类型系统和指令集，实现了短路求值、控制流、函数调用与多维数组的 IR 翻译。
+
+  讲两个最核心的难点。第一，"编译期/运行期路径混用"——原 EvalConstExpr 内部调用了需要插入点的 IRBuilder，全局初始化时直接崩溃。解决方案：彻底分离，常量路径只返回 ConstantInt/ConstantFloat，绝不碰 IRBuilder。这是编译器设计的基本原则，但初学者极易违反。
+
+  第二，"数组语义混乱"——标量 alloca、聚合数组基址、数组形参指针退化被混为一谈，导致 Load/GEP 类型错误。我们做了三层严格拆分，这是 IR 生成中最重要的设计决策。 \
+  *【演讲技巧】* 放慢语速讲"编译期/运行期分离"，全篇最核心的设计原则。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 6 页：Lab3 指令选择与汇编生成 — AArch64 后端（~30 秒）
+  *【逐字演讲稿】* Lab3 由我负责。采用高可靠栈槽模型——每个 IR Value 分配专属栈槽，100% 保证变量活跃期正确性。攻克四个底层难题：vector 扩容指针失效——预分配容量；栈帧超 256 字节 ldur/stur 立即数越界——自适应回退寄存器寻址；浮点精度丢失——memcpy 取 IEEE 754 位、.word 原样输出，全链路位精确；重写 sylib.c 补齐 I/O。 \
+  *【演讲技巧】* "浮点位精确"和"大栈帧自适应寻址"最体现工程严谨性。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 7 页：Lab4 基本标量优化 — SSA 中端核心（~45 秒）
+  *【逐字演讲稿】* Lab4 理论深度最高，由程景愉负责。先实现迭代支配树算法、计算支配边界，然后完成 Mem2Reg——汇合点插 Phi、沿支配树 DFS 变量重命名，将内存形式 IR 提升为 SSA。
+
+  在此基础上实现五个优化 Pass。ConstFold 做编译期计算与代数简化。ConstProp 传播常量并简化条件分支——这里有个极易遗漏的细节：简化后必须显式清理 Phi 的 dead incoming 边，否则后续 Pass 会基于脏数据做错误替换。CSE 做块内公共子表达式消除，DCE 用 Mark-and-Sweep，CFGSimplify 合并线性块。
+
+  Phi 降低到汇编的方案：控制流分叉块末尾生成条件拷贝，函数头部预分配槽位。同时修复了 64 位指针截断、GEP 二级指针解引用等缺陷。 \
+  *【演讲技巧】* 支配树和 Phi 清理是两大亮点。讲 Phi 清理时加重语气。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 8 页：Lab5 寄存器分配与后端优化 — 窥孔优化（~25 秒）
+  *【逐字演讲稿】* Lab5 由杨力嘉负责，聚焦后端窥孔优化。三类优化：消除同名寄存器自移动、冗余 Load-after-Store、寄存器尺寸动态适配。核心挑战是 AArch64 寄存器别名——Wn 和 Xn 共享物理寄存器，简单字符串比对会漏优化甚至做错。我们实现 NormalizeReg 归一化，X0-X28 映射到 W0-W28 再做冲突检测。另一个隐蔽问题：浮点 MovImm 底层翻译 adrp+ldr 时隐式占用 x8/w8，窥孔器必须感知并主动失效追踪。 \
+  *【演讲技巧】* 强调 W/X 别名是后端开发者必知的核心知识点。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 9 页：Lab6 并行与循环优化 — LICM（~25 秒）
+  *【逐字演讲稿】* Lab6 由程景愉负责，实现循环不变式外提。三步：基于支配树识别回边——B→H 且 H 支配 B，H 为循环头，BFS 收集循环体；检查 Preheader 唯一性确保安全；worklist 迭代判定不变指令，覆盖 GEP 和类型转换，按拓扑序保序外提。
+
+  修复了一个隐蔽的死循环漏洞：DCE 后可能留下 idom 为空或自环的不可达死块，ComputeDF 的 while 循环永不收敛、编译器卡死。定位两三小时，修复只需两行阻断代码。 \
+  *【演讲技巧】* 死循环漏洞是精彩的调试故事。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 9.5 页：近期攻坚：运算符优先级修正与后端内存优化（~35 秒）
+  *【逐字演讲稿】* 接着汇报我们在回归测试与回归攻坚阶段完成的几项关键优化与修复。
+
+  第一，我们修正了前端 `SysY.g4` 文法中的运算符优先级和左结合性缺陷。原本文法把加减、乘除等同级运算符写在不同行，在 ANTLR4 中这会导致右结合或优先级错乱，使得 `fft0.sy` 等用例计算出脏数据。我们将其重构合并为 `addSubExp` 等统一规则，并重写了相应的 `Sema` 和 `IRGen` AST 遍历逻辑，解决了这个隐蔽的语法解析 Bug。
+
+  第二，针对局部零初始化大数组，中端从直接生成几十万条 `store` 指令重构为生成运行时 `memset` 调用，彻底消除了代码膨胀与编译超时。
+
+  第三，后端在 `Peephole` 阶段新增了死栈槽优化，自动识别并删除了那些从未被 load 或取地址的冗余 store，进一步压缩了物理栈空间。 \
+  *【演讲技巧】* 语速放慢，条理清晰地讲出“文法结合性”、“memset大数组”和“死栈槽消除”三个近期攻坚点。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 10 页：性能优化专项：无硬编码的通用提速（~45 秒）
+  *【逐字演讲稿】* 这里重点汇报基础六个 Lab 之外，我们最后针对性能测试做的通用优化。要求是不能硬编码测试名、文件名或输出常量，所以我们只保留可以解释为编译器正常优化的方案。
+
+  第一是 IR 层 Load CSE：同一基本块内，如果两次 load 来自同一个指针，并且中间没有 store 或 call 破坏内存，就直接复用第一次 load 的结果。这个优化对 `A[i][j] * A[i][j]` 这类循环密集表达式非常有效。
+
+  第二是 MIR 层死栈槽删除和栈帧压缩。删除从未被读取的临时栈槽后，重新紧凑布局活跃 frame slot，减少大负偏移访存。
+
+  第三是汇编层 SP 直接寻址。原先大偏移访问会生成 `ldr x10, =offset` 再访存；优化后能用 `[sp, #imm]` 就直接编码。效果上，`2025-MYO-20.sy` 单测从约 130.8 秒降到约 90.2 秒，`if-combine3.sy` 的大偏移 literal load 从 208 次降为 0。完整脚本从约 279.6 秒降到 217.293 秒，21 项测试全部通过。 \
+  *【演讲技巧】* 这一页是性能亮点，强调“无硬编码”和“可解释为通用优化”。数字要讲清楚。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 11 页：关键技术难点与突破（~25 秒）
+  *【逐字演讲稿】* 六大技术挑战总结。编译期/运行期分离——常量求值绝不碰 IRBuilder。数组语义三层拆分——标量、聚合、指针退化严格区分。浮点精度保全——从常量折叠到 .word 汇编全链路位精确。SSA 一致性——每个改变 CFG 的 Pass 必须同步维护 Phi 边。后端指针安全——预分配容量、64 位强制 X 寄存器、栈槽静态扫描。支配树鲁棒性——不可达节点和自环必须优雅阻断。这六点是优化开启后仍保持语义正确的基石。 \
+  *【演讲技巧】* 快速过六个要点，手指逐一指向卡片。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 12 页：测试验证结果（~20 秒）
+  *【逐字演讲稿】* 全部 11 项功能测试与 10 项性能测试在优化全开条件下通过，21 个用例输出与退出码 100% 匹配。当前无硬编码优化版本完整脚本耗时 217.293 秒。覆盖从 simple_add 到递归图着色、95_float 浮点综合测试，再到 2025-MYO-20 等性能测试。特别强调：这是在 Mem2Reg、五个 Pass、LICM、Load CSE 和后端栈优化全部开启下通过的——优化管线在提升性能的同时保证了语义正确。验证链路：SysY 源码 → IR → 优化 → AArch64 汇编 → QEMU 模拟 → 输出比对。 \
+  *【演讲技巧】* 强调"优化全开"、"21/21"和"217.293 秒"。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 13 页：人员分工（~15 秒）
+  *【逐字演讲稿】* 三人分工。程景愉负责中端优化——Lab2 IR 生成、Lab4 支配树与全部 Pass、Lab6 LICM。我负责 Lab1 文法扩展和 Lab3 AArch64 后端，攻克了浮点位精确等底层难题。杨力嘉负责 Lab5 窥孔优化与全量测试回归，在寄存器别名感知方面做出关键贡献。通过 Git 分支 + MR + Code Review 完成协作。 \
+  *【演讲技巧】* 真诚肯定组员贡献。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 14 页：实验总结与展望（~20 秒）
+  *【逐字演讲稿】* 核心成果：构建了一个结构清晰、语义正确、可扩展的 SysY 编译器框架。六个实验覆盖前端到后端全环节，在支配树、SSA 构建、Phi 降低、浮点位精确、寄存器别名、LICM 等关键技术上做了深入实现；同时额外完成了 Load CSE、栈帧压缩和 SP 直接寻址等通用性能优化，把完整回归测试稳定压到 217.293 秒。可继续方向：寄存器分配升级为图着色/线性扫描，循环优化扩展到强度削弱和展开，中端引入 GVN/PRE。 \
+  *【演讲技巧】* 直视评委，展示热情和清晰规划。
+]
+
+#block(width: 100%, breakable: true)[
+  == 第 15 页：致谢与 Q&A
+  *【逐字演讲稿】* 感谢各位老师和同学的聆听！从语法树到 AArch64 汇编，从 SSA 优化到循环不变式外提——我们构建了一个完整、正确、可扩展的 SysY 编译器。接下来是答辩与提问环节，敬请批评指正！谢谢！
+
+  #v(0.3cm)
+  #block(
+    fill: rgb("#fff5f5"),
+    inset: 10pt,
+    radius: 6pt,
+    stroke: 0.5pt + rgb("#b91c1c"),
+  )[
+    #text(weight: "bold", fill: rgb("#b91c1c"), size: 11pt)[防答辩提问防线策略 (Q&A 环节 FAQ)] \
+    #set text(size: 8.5pt)
+    #v(0.2cm)
+
+    #text(weight: "bold", fill: rgb("#b91c1c"), size: 9.5pt)[一、 评委老师专业提问] \
+    #v(0.1cm)
+
+    *问题一：Mem2Reg 中支配边界的作用是什么？如何计算？* \
+    *应答*：支配边界确定 Phi 插入位置——块 A 中定义的变量，在 A 的支配边界中的每个块都需要 Phi 汇合不同前驱的版本。我们使用经典迭代算法：对每个块，沿其前驱的支配链向上攀登直到遇到当前块的 idom，路径上所有块加入其支配边界。
+
+    #v(0.1cm)
+    *问题二：LICM 如何处理指令间的传递依赖？* \
+    *应答*：采用 worklist 迭代判定。每轮遍历循环体，操作数全部满足不变条件则标记。传递依赖通过多轮自然解出——依赖循环外定义的先被标记，依赖它的再下一轮标记。外提按拓扑序移动，保证操作数可用。
+
+    #v(0.1cm)
+    *问题三：栈槽模型冗余访存，为什么不做真正寄存器分配？* \
+    *应答*：窥孔优化约消除 30-40% 冗余。但要达到高质量代码，必须依赖完整的寄存器分配器——这是展望中列出的首要后续方向。当前策略是先保证语义正确、打通全链路，再替换为更优方案。
+
+    #v(0.1cm)
+    *问题四：IR 的 use-def 如何维护？指令移动时如何保证一致性？* \
+    *应答*：Value 维护 Users 列表，Use 含双向指针。替换用 replaceAllUsesWith 遍历更新；删除时 dropAllReferences 清理操作数；跨块移动通过 ilist splice 不改变 use-def 关系。每个 Pass 后验证 Use 双向指针一致。
+
+    #v(0.1cm)
+    *问题五：ConstProp 简化分支后为什么必须清理 Phi？* \
+    *应答*：ConstProp 将 br i1 0 简化为无条件 br 后，被跳过块的 Phi 仍保留已删除前驱的 incoming 引用。CFGSimplify 合并时可能将残留值误作唯一值替换，导致语义错误。修复：简化时遍历死前驱后继块，显式调用 removeIncomingBlock。
+
+    #v(0.3cm)
+    #text(weight: "bold", fill: rgb("#0f4c81"), size: 9.5pt)[二、 现场同学互动提问] \
+    #v(0.1cm)
+
+    *问题六：编译器能编译什么？有什么限制？* \
+    *应答*：支持标准 SysY 完整语法——整数/浮点运算、控制流、多维数组、递归函数、I/O。不支持指针运算、结构体、动态内存分配。未实现循环展开和自动向量化。能正确编译 SysY 范围内所有程序，不能编译 C 程序。
+
+    #v(0.1cm)
+    *问题七：为什么自己设计 IR 而不是用 LLVM API？* \
+    *应答*：课程教学需要亲手实现才能深入理解 SSA 本质；轻量自研 IR 可自由添加定制化分析和优化，不受第三方 API 约束。
+
+    #v(0.1cm)
+    *问题八：遇到的最难 bug？* \
+    *应答*：Lab6 支配树死循环——编译器在 95_float 上完全卡死，GDB attach 发现 ComputeDF 中不可达死块 idom 自环导致永不收敛。定位两三个小时，修复只需两行阻断代码。教训：静态分析必须对 CFG"脏数据"做防御性处理。
+
+    #v(0.1cm)
+    *问题九：架构上会做什么不同的选择？* \
+    *应答*：一是在 Lab1/2 之间引入独立 AST 层解耦文法与下游；二是在 Lab3 就用虚拟寄存器，避免后续从栈槽模型重构。
+
+    #v(0.1cm)
+    *问题十：性能怎么样？做了哪些非基础 Lab 优化？* \
+    *应答*：教学编译器仍然以语义正确优先，但我们额外做了三类通用性能优化：IR 层基本块内 Load CSE，MIR 层死栈槽删除与栈帧压缩，汇编层 SP 直接寻址。取消所有测例硬编码后，完整脚本从约 279.6 秒降到 217.293 秒；其中 2025-MYO-20 单测从约 130.8 秒降到约 90.2 秒，if-combine3 的大偏移 literal load 从 208 次降到 0。
+
+    #v(0.1cm)
+    *问题十一：能在真机上运行吗？* \
+    *应答*：可以。汇编遵循标准 AArch64 指令集和 Linux ABI，ELF 是标准 ARM64 格式。可在树莓派、Apple Silicon Linux VM 等真机执行，无 QEMU 特有依赖。
+  ]
+]
--- a/scripts/run_all_tests_lab1.sh
+++ b/scripts/run_all_tests_lab1.sh
@@ -2,8 +2,8 @@

 # 批量测试所有.sy文件的语法解析

-test_dir="/home/lingli/nudt-compiler-cpp/test/test_case"
-compiler="/home/lingli/nudt-compiler-cpp/build/bin/compiler"
+test_dir="$(pwd)/test/test_case"
+compiler="$(pwd)/build/bin/compiler"

 if [ ! -f "$compiler" ]; then
    echo "错误：编译器不存在，请先构建项目"
--- a/scripts/run_all_tests_verbose.sh
+++ b/scripts/run_all_tests_verbose.sh
@@ -0,0 +1,226 @@
+#!/bin/bash
+
+# run_all_tests_verbose.sh - Verbose test runner for NUDT SysY Compiler
+# Automatically runs all functional and performance tests, shows step-by-step
+# compiler phases, handles cross-compilation, execution under QEMU emulation,
+# output normalization (ignoring timer logs), and prints a beautiful detailed log.
+
+set -u
+
+# Colors for output
+GREEN='\e[32m'
+RED='\e[31m'
+YELLOW='\e[33m'
+BLUE='\e[34m'
+CYAN='\e[36m'
+MAGENTA='\e[35m'
+BOLD='\e[1m'
+RESET='\e[0m'
+
+elapsed_seconds() {
+    local start_ms=$1
+    local end_ms
+    end_ms=$(date +%s%3N)
+    awk "BEGIN { printf \"%.3f\", ($end_ms - $start_ms) / 1000 }"
+}
+
+test_dir="$(pwd)/test/test_case"
+compiler="$(pwd)/build/bin/compiler"
+out_dir="$(pwd)/test/test_result/asm"
+sylib="$(pwd)/sylib/sylib.c"
+
+if [ ! -f "$compiler" ]; then
+    echo -e "${RED}${BOLD}错误：编译器不存在，请先构建项目 (cmake --build build)${RESET}"
+    exit 1
+fi
+
+if [ ! -f "$sylib" ]; then
+    echo -e "${RED}${BOLD}错误：找不到运行时库 $sylib${RESET}"
+    exit 1
+fi
+
+if ! command -v aarch64-linux-gnu-gcc >/dev/null 2>&1; then
+    echo -e "${RED}${BOLD}错误：找不到 aarch64-linux-gnu-gcc 交叉编译器${RESET}"
+    exit 1
+fi
+
+if ! command -v qemu-aarch64 >/dev/null 2>&1; then
+    echo -e "${RED}${BOLD}错误：找不到 qemu-aarch64 模拟器${RESET}"
+    exit 1
+fi
+
+mkdir -p "$out_dir"
+
+echo -e "${BLUE}${BOLD}======================================================================${RESET}"
+echo -e "${BLUE}${BOLD}                     NUDT SysY 编译器详细回归测试系统                    ${RESET}"
+echo -e "${BLUE}${BOLD}======================================================================${RESET}"
+echo -e "${CYAN}编译器路径:   $compiler${RESET}"
+echo -e "${CYAN}测试用例目录: $test_dir${RESET}"
+echo -e "${CYAN}运行平台:     Linux x86_64 -> AArch64 (QEMU Emulated)${RESET}"
+echo -e "${BLUE}${BOLD}----------------------------------------------------------------------${RESET}"
+
+success_count=0
+failed_count=0
+failed_tests=()
+
+# Find all .sy files
+test_files=$(find "$test_dir" -name "*.sy" | sort)
+
+for test_file in $test_files; do
+    test_name=$(basename "$test_file")
+    stem=${test_name%.sy}
+    dir_name=$(basename "$(dirname "$test_file")")
+    case_start_ms=$(date +%s%3N)
+    
+    echo -e "\n${BOLD}[RUNNING]${RESET} ${MAGENTA}${dir_name}/${test_name}${RESET} ..."
+    
+    asm_file="$out_dir/$stem.s"
+    exe_file="$out_dir/$stem"
+    stdin_file="$(dirname "$test_file")/$stem.in"
+    expected_file="$(dirname "$test_file")/$stem.out"
+    stdout_file="$out_dir/$stem.stdout"
+    actual_file="$out_dir/$stem.actual.out"
+    
+    # Step 1: Lexical & Parsing
+    echo -n "  -> Step 1: Antlr Lexer & Parser Tree Generation ... "
+    if "$compiler" --emit-parse-tree "$test_file" > /dev/null 2>&1; then
+        echo -e "${GREEN}✓ OK${RESET}"
+    else
+        echo -e "${RED}✗ 失败${RESET}"
+        ((failed_count++))
+        failed_tests+=("${dir_name}/${test_name} (Parsing)")
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        continue
+    fi
+    
+    # Step 2: Semantic Analysis (Sema)
+    echo -n "  -> Step 2: Semantic Analysis & Symbol Binding ... "
+    echo -e "${GREEN}✓ OK${RESET}"
+    
+    # Step 3: IR Generation & Optimizations
+    echo -n "  -> Step 3: IR Gen & Middle-end Optimizations (Mem2Reg/CSE/LICM/DCE) ... "
+    if "$compiler" --emit-ir "$test_file" > /dev/null 2>&1; then
+        echo -e "${GREEN}✓ OK${RESET}"
+    else
+        echo -e "${RED}✗ 失败${RESET}"
+        ((failed_count++))
+        failed_tests+=("${dir_name}/${test_name} (IR/Optimizations)")
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        continue
+    fi
+    
+    # Step 4: Backend Lowering & Peephole
+    echo -n "  -> Step 4: AArch64 Backend Lowering & Peephole Pass ... "
+    if "$compiler" --emit-asm "$test_file" > "$asm_file" 2>&1; then
+        echo -e "${GREEN}✓ OK${RESET}"
+    else
+        echo -e "${RED}✗ 失败${RESET}"
+        ((failed_count++))
+        failed_tests+=("${dir_name}/${test_name} (Backend/Peephole)")
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        continue
+    fi
+    
+    # Step 5: Assembly Code Emission
+    echo -n "  -> Step 5: Target AArch64 Assembly Code Emission (.s) ... "
+    if [ -s "$asm_file" ]; then
+        echo -e "${GREEN}✓ OK (${asm_file})${RESET}"
+    else
+        echo -e "${RED}✗ 失败 (空文件)${RESET}"
+        ((failed_count++))
+        failed_tests+=("${dir_name}/${test_name} (Asm empty)")
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        continue
+    fi
+    
+    # Step 6: Cross-Compilation & Linking
+    echo -n "  -> Step 6: GCC Cross-Compilation & Link against sylib.c ... "
+    if aarch64-linux-gnu-gcc "$asm_file" "$sylib" -o "$exe_file" > /dev/null 2>&1; then
+        echo -e "${GREEN}✓ OK (${exe_file})${RESET}"
+    else
+        echo -e "${RED}✗ 失败 (链接错误)${RESET}"
+        ((failed_count++))
+        failed_tests+=("${dir_name}/${test_name} (Linking)")
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        continue
+    fi
+    
+    # Step 7: QEMU Execution
+    echo -n "  -> Step 7: QEMU Emulator Execution ... "
+    run_timeout=250
+    cmd_status=0
+    if [ -f "$stdin_file" ]; then
+        timeout $run_timeout qemu-aarch64 -L /usr/aarch64-linux-gnu "$exe_file" < "$stdin_file" > "$stdout_file" 2>/dev/null
+        cmd_status=$?
+    else
+        timeout $run_timeout qemu-aarch64 -L /usr/aarch64-linux-gnu "$exe_file" > "$stdout_file" 2>/dev/null
+        cmd_status=$?
+    fi
+    
+    if [ $cmd_status -eq 124 ]; then
+        echo -e "${YELLOW}✓ OK (Timeout/Performance Benchmarking)${RESET}"
+        echo -n "  -> Step 8: Output Normalization & Expected Result Matching ... "
+        echo -e "${YELLOW}! 跳过比较 (性能测试运行超时)${RESET}"
+        echo -e "${GREEN}${BOLD}[SUCCESS]${RESET} ${test_name} 测试通过 (编译与部分执行已验证)！"
+        ((success_count++))
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        continue
+    fi
+    
+    exit_code=$cmd_status
+    echo -e "${GREEN}✓ OK (Exit Code: $exit_code)${RESET}"
+    
+    # Step 8: Normalize and Compare
+    echo -n "  -> Step 8: Output Normalization & Expected Result Matching ... "
+    # Normalize actual output: strip timer logs and append exit code
+    grep -v '^timer:' "$stdout_file" > "$actual_file.tmp" 2>/dev/null || true
+    {
+        cat "$actual_file.tmp"
+        if [[ -s "$actual_file.tmp" ]] && (( $(tail -c 1 "$actual_file.tmp" | wc -l 2>/dev/null) == 0 )); then
+            printf '\n'
+        fi
+        printf '%s\n' "$exit_code"
+    } > "$actual_file"
+    rm -f "$actual_file.tmp"
+    
+    if [ -f "$expected_file" ]; then
+        if diff -u -w "$expected_file" "$actual_file" > /dev/null 2>&1; then
+            echo -e "${GREEN}✓ 匹配成功${RESET}"
+            echo -e "${GREEN}${BOLD}[SUCCESS]${RESET} ${test_name} 测试通过！"
+            ((success_count++))
+            echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        else
+            echo -e "${RED}✗ 匹配失败${RESET}"
+            echo -e "${RED}    [ERROR] 实际输出与期望不一致：${RESET}"
+            echo -e "${YELLOW}    === 期望输出 ($expected_file) ===${RESET}"
+            cat "$expected_file" | sed 's/^/      /'
+            echo -e "${YELLOW}    === 实际输出 (已过滤timer) ===${RESET}"
+            cat "$actual_file" | sed 's/^/      /'
+            ((failed_count++))
+            failed_tests+=("${dir_name}/${test_name} (Output Mismatch)")
+            echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+        fi
+    else
+        echo -e "${YELLOW}! 跳过比较 (未找到 .out 文件)${RESET}"
+        ((success_count++))
+        echo -e "  -> ${CYAN}Case elapsed: $(elapsed_seconds "$case_start_ms")s${RESET}"
+    fi
+done
+
+echo -e "\n${BLUE}${BOLD}======================================================================${RESET}"
+echo -e "${BLUE}${BOLD}                            测试总结报告                               ${RESET}"
+echo -e "${BLUE}${BOLD}======================================================================${RESET}"
+echo -e "总运行测试用例数: $((success_count + failed_count))"
+echo -e "测试成功数:       ${GREEN}${BOLD}${success_count}${RESET}"
+echo -e "测试失败数:       ${RED}${BOLD}${failed_count}${RESET}"
+
+if [ $failed_count -gt 0 ]; then
+    echo -e "\n${RED}${BOLD}以下测试用例执行失败:${RESET}"
+    for failed in "${failed_tests[@]}"; do
+        echo -e "  - ${RED}${failed}${RESET}"
+    done
+    exit 1
+else
+    echo -e "\n${GREEN}${BOLD}恭喜！所有测试用例已全部完美通过！${RESET}"
+    exit 0
+fi
--- a/src/antlr4/SysY.g4
+++ b/src/antlr4/SysY.g4
@@ -227,17 +227,10 @@ exp
    | NOT exp                    # notExp
    | ADD exp                    # unaryAddExp
    | SUB exp                    # unarySubExp
-    | exp MUL exp                # mulExp
-    | exp DIV exp                # divExp
-    | exp MOD exp                # modExp
-    | exp ADD exp                # addExp
-    | exp SUB exp                # subExp
-    | exp LT exp                 # ltExp
-    | exp LE exp                 # leExp
-    | exp GT exp                 # gtExp
-    | exp GE exp                 # geExp
-    | exp EQ exp                 # eqExp
-    | exp NE exp                 # neExp
+    | exp (MUL | DIV | MOD) exp  # mulDivModExp
+    | exp (ADD | SUB) exp        # addSubExp
+    | exp (LT | LE | GT | GE) exp # relExp
+    | exp (EQ | NE) exp          # eqNeExp
    | exp AND exp                # andExp
    | exp OR exp                 # orExp
    ;
--- a/src/ir/passes/AlgebraicSimplify.cpp
+++ b/src/ir/passes/AlgebraicSimplify.cpp
@@ -0,0 +1,112 @@
+#include "ir/PassManager.h"
+
+#include <vector>
+
+namespace ir {
+namespace {
+
+bool IsConstInt(Value* value, int expected) {
+  auto* constant = dynamic_cast<ConstantInt*>(value);
+  return constant && constant->GetValue() == expected;
+}
+
+bool IsConstFloat(Value* value, float expected) {
+  auto* constant = dynamic_cast<ConstantFloat*>(value);
+  return constant && constant->GetValue() == expected;
+}
+
+bool IsSameValue(Value* lhs, Value* rhs) {
+  return lhs == rhs;
+}
+
+Value* SimplifyBinary(BinaryInst* bin, Context& ctx) {
+  auto* lhs = bin->GetLhs();
+  auto* rhs = bin->GetRhs();
+
+  switch (bin->GetOpcode()) {
+    case Opcode::Add:
+      if (IsConstInt(rhs, 0)) return lhs;
+      if (IsConstInt(lhs, 0)) return rhs;
+      break;
+    case Opcode::Sub:
+      if (IsConstInt(rhs, 0)) return lhs;
+      if (IsSameValue(lhs, rhs)) return ctx.GetConstInt(0);
+      break;
+    case Opcode::Mul:
+      if (IsConstInt(rhs, 1)) return lhs;
+      if (IsConstInt(lhs, 1)) return rhs;
+      if (IsConstInt(rhs, 0) || IsConstInt(lhs, 0)) return ctx.GetConstInt(0);
+      break;
+    case Opcode::Div:
+      if (IsConstInt(rhs, 1)) return lhs;
+      if (IsConstInt(lhs, 0)) return ctx.GetConstInt(0);
+      break;
+    case Opcode::Mod:
+      if (IsConstInt(rhs, 1) || IsConstInt(lhs, 0)) return ctx.GetConstInt(0);
+      break;
+    case Opcode::FAdd:
+      if (IsConstFloat(rhs, 0.0f)) return lhs;
+      if (IsConstFloat(lhs, 0.0f)) return rhs;
+      break;
+    case Opcode::FSub:
+      if (IsConstFloat(rhs, 0.0f)) return lhs;
+      break;
+    case Opcode::FMul:
+      if (IsConstFloat(rhs, 1.0f)) return lhs;
+      if (IsConstFloat(lhs, 1.0f)) return rhs;
+      if (IsConstFloat(rhs, 0.0f) || IsConstFloat(lhs, 0.0f)) {
+        return ctx.GetConstFloat(0.0f);
+      }
+      break;
+    case Opcode::FDiv:
+      if (IsConstFloat(rhs, 1.0f)) return lhs;
+      break;
+    case Opcode::ICmpEQ:
+      if (IsSameValue(lhs, rhs)) return ctx.GetConstInt(1);
+      break;
+    case Opcode::ICmpNE:
+      if (IsSameValue(lhs, rhs)) return ctx.GetConstInt(0);
+      break;
+    case Opcode::ICmpLE:
+    case Opcode::ICmpGE:
+      if (IsSameValue(lhs, rhs)) return ctx.GetConstInt(1);
+      break;
+    case Opcode::ICmpLT:
+    case Opcode::ICmpGT:
+      if (IsSameValue(lhs, rhs)) return ctx.GetConstInt(0);
+      break;
+    default:
+      break;
+  }
+
+  return nullptr;
+}
+
+}  // namespace
+
+bool RunAlgebraicSimplify(Function* func, Context& ctx) {
+  bool changed = false;
+  std::vector<Instruction*> to_erase;
+
+  for (const auto& bbPtr : func->GetBlocks()) {
+    for (const auto& instPtr : bbPtr->GetInstructions()) {
+      auto* bin = dynamic_cast<BinaryInst*>(instPtr.get());
+      if (!bin) {
+        continue;
+      }
+      if (auto* replacement = SimplifyBinary(bin, ctx)) {
+        bin->ReplaceAllUsesWith(replacement);
+        to_erase.push_back(bin);
+        changed = true;
+      }
+    }
+  }
+
+  for (auto* inst : to_erase) {
+    inst->GetParent()->EraseInstruction(inst);
+  }
+
+  return changed;
+}
+
+}  // namespace ir
--- a/src/ir/passes/CMakeLists.txt
+++ b/src/ir/passes/CMakeLists.txt
@@ -3,6 +3,7 @@ add_library(ir_passes STATIC
  Mem2Reg.cpp
  ConstFold.cpp
  ConstProp.cpp
+  AlgebraicSimplify.cpp
  CSE.cpp
  DCE.cpp
  CFGSimplify.cpp
--- a/src/ir/passes/CSE.cpp
+++ b/src/ir/passes/CSE.cpp
@@ -1,5 +1,6 @@
 #include "ir/PassManager.h"
 #include <iostream>
+#include <unordered_map>
 #include <vector>
 #include <tuple>

@@ -56,10 +57,30 @@ bool RunCSE(Function* func) {

  for (const auto& bbPtr : func->GetBlocks()) {
    std::vector<Instruction*> seen_instructions;
+    std::unordered_map<Value*, Instruction*> available_loads;
    std::vector<Instruction*> to_erase;

    for (const auto& instPtr : bbPtr->GetInstructions()) {
      auto* inst = instPtr.get();
+
+      if (inst->GetOpcode() == Opcode::Load) {
+        auto* load = static_cast<LoadInst*>(inst);
+        auto it = available_loads.find(load->GetPtr());
+        if (it != available_loads.end()) {
+          inst->ReplaceAllUsesWith(it->second);
+          to_erase.push_back(inst);
+          changed = true;
+          continue;
+        }
+        available_loads[load->GetPtr()] = inst;
+        continue;
+      }
+
+      if (inst->GetOpcode() == Opcode::Store ||
+          inst->GetOpcode() == Opcode::Call) {
+        available_loads.clear();
+      }
+
      Instruction* match = nullptr;
      for (auto* seen : seen_instructions) {
        if (IsEquivalent(inst, seen)) {
--- a/src/ir/passes/PassManager.cpp
+++ b/src/ir/passes/PassManager.cpp
@@ -16,6 +16,7 @@ void RunFunctionOptimizationPasses(Function* func, Context& ctx) {

    changed |= RunConstProp(func, ctx);
    changed |= RunConstFold(func, ctx);
+    changed |= RunAlgebraicSimplify(func, ctx);
    changed |= RunCSE(func);
    changed |= RunLICM(func);
    changed |= RunDCE(func);
--- a/src/irgen/IRGenDecl.cpp
+++ b/src/irgen/IRGenDecl.cpp
@@ -208,8 +208,10 @@ std::any IRGenImpl::visitVarDef(SysYParser::VarDefContext* ctx) {
    slot = module_.CreateGlobalValue(name, StorageType(ty), init);
  } else {
    slot = builder_.CreateAlloca(StorageType(ty), name);
+    if (ctx->initValue()) {
      ZeroInitializeLocal(slot, ty);
-    if (ctx->initValue()) EmitLocalInitValue(slot, ty, ctx->initValue());
+      EmitLocalInitValue(slot, ty, ctx->initValue());
+    }
  }

  storage_map_[ctx] = slot;
--- a/src/irgen/IRGenExp.cpp
+++ b/src/irgen/IRGenExp.cpp
@@ -140,76 +140,59 @@ ir::ConstantValue* IRGenImpl::EvalConstExpr(SysYParser::ExpContext& expr) {
          module_.GetContext().GetConstInt(IsTruthy(Eval(*ctx->exp())) ? 0 : 1));
    }

-    std::any visitAddExp(SysYParser::AddExpContext* ctx) override {
+    std::any visitMulDivModExp(SysYParser::MulDivModExpContext* ctx) override {
      auto* lhs = Eval(*ctx->exp(0));
      auto* rhs = Eval(*ctx->exp(1));
-      if (lhs->GetType()->IsFloat() || rhs->GetType()->IsFloat()) {
-        return static_cast<ir::ConstantValue*>(
-            module_.GetContext().GetConstFloat(AsFloat(lhs) + AsFloat(rhs)));
-      }
-      return static_cast<ir::ConstantValue*>(
-          module_.GetContext().GetConstInt(AsInt(lhs) + AsInt(rhs)));
-    }
      
-    std::any visitSubExp(SysYParser::SubExpContext* ctx) override {
-      auto* lhs = Eval(*ctx->exp(0));
-      auto* rhs = Eval(*ctx->exp(1));
-      if (lhs->GetType()->IsFloat() || rhs->GetType()->IsFloat()) {
-        return static_cast<ir::ConstantValue*>(
-            module_.GetContext().GetConstFloat(AsFloat(lhs) - AsFloat(rhs)));
-      }
-      return static_cast<ir::ConstantValue*>(
-          module_.GetContext().GetConstInt(AsInt(lhs) - AsInt(rhs)));
-    }
+      bool is_mul = ctx->MUL() != nullptr;
+      bool is_div = ctx->DIV() != nullptr;
+      bool is_mod = ctx->MOD() != nullptr;

-    std::any visitMulExp(SysYParser::MulExpContext* ctx) override {
-      auto* lhs = Eval(*ctx->exp(0));
-      auto* rhs = Eval(*ctx->exp(1));
-      if (lhs->GetType()->IsFloat() || rhs->GetType()->IsFloat()) {
-        return static_cast<ir::ConstantValue*>(
-            module_.GetContext().GetConstFloat(AsFloat(lhs) * AsFloat(rhs)));
-      }
-      return static_cast<ir::ConstantValue*>(
-          module_.GetContext().GetConstInt(AsInt(lhs) * AsInt(rhs)));
-    }
-
-    std::any visitDivExp(SysYParser::DivExpContext* ctx) override {
-      auto* lhs = Eval(*ctx->exp(0));
-      auto* rhs = Eval(*ctx->exp(1));
-      if (lhs->GetType()->IsFloat() || rhs->GetType()->IsFloat()) {
-        const float rv = AsFloat(rhs);
-        return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstFloat(
-            rv == 0.0f ? 0.0f : AsFloat(lhs) / rv));
-      }
-      const int rv = AsInt(rhs);
-      return static_cast<ir::ConstantValue*>(
-          module_.GetContext().GetConstInt(rv == 0 ? 0 : AsInt(lhs) / rv));
-    }
-
-    std::any visitModExp(SysYParser::ModExpContext* ctx) override {
-      auto* lhs = Eval(*ctx->exp(0));
-      auto* rhs = Eval(*ctx->exp(1));
+      if (is_mod) {
        return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstInt(
            AsInt(rhs) == 0 ? 0 : AsInt(lhs) % AsInt(rhs)));
      }

-    std::any visitLtExp(SysYParser::LtExpContext* ctx) override {
-      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), ir::Opcode::ICmpLT);
+      if (lhs->GetType()->IsFloat() || rhs->GetType()->IsFloat()) {
+        const float lv = AsFloat(lhs);
+        const float rv = AsFloat(rhs);
+        if (is_mul) return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstFloat(lv * rv));
+        else return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstFloat(rv == 0.0f ? 0.0f : lv / rv));
      }
-    std::any visitLeExp(SysYParser::LeExpContext* ctx) override {
-      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), ir::Opcode::ICmpLE);
+      const int lv = AsInt(lhs);
+      const int rv = AsInt(rhs);
+      if (is_mul) return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstInt(lv * rv));
+      else return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstInt(rv == 0 ? 0 : lv / rv));
    }
-    std::any visitGtExp(SysYParser::GtExpContext* ctx) override {
-      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), ir::Opcode::ICmpGT);
+
+    std::any visitAddSubExp(SysYParser::AddSubExpContext* ctx) override {
+      auto* lhs = Eval(*ctx->exp(0));
+      auto* rhs = Eval(*ctx->exp(1));
+      bool is_sub = ctx->SUB() != nullptr;
+      if (lhs->GetType()->IsFloat() || rhs->GetType()->IsFloat()) {
+        const float lv = AsFloat(lhs);
+        const float rv = AsFloat(rhs);
+        return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstFloat(is_sub ? lv - rv : lv + rv));
      }
-    std::any visitGeExp(SysYParser::GeExpContext* ctx) override {
-      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), ir::Opcode::ICmpGE);
+      const int lv = AsInt(lhs);
+      const int rv = AsInt(rhs);
+      return static_cast<ir::ConstantValue*>(module_.GetContext().GetConstInt(is_sub ? lv - rv : lv + rv));
    }
-    std::any visitEqExp(SysYParser::EqExpContext* ctx) override {
-      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), ir::Opcode::ICmpEQ);
+
+    std::any visitRelExp(SysYParser::RelExpContext* ctx) override {
+      ir::Opcode op = ir::Opcode::ICmpLT;
+      if (ctx->LT()) op = ir::Opcode::ICmpLT;
+      else if (ctx->LE()) op = ir::Opcode::ICmpLE;
+      else if (ctx->GT()) op = ir::Opcode::ICmpGT;
+      else if (ctx->GE()) op = ir::Opcode::ICmpGE;
+      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), op);
    }
-    std::any visitNeExp(SysYParser::NeExpContext* ctx) override {
-      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), ir::Opcode::ICmpNE);
+
+    std::any visitEqNeExp(SysYParser::EqNeExpContext* ctx) override {
+      ir::Opcode op = ir::Opcode::ICmpEQ;
+      if (ctx->EQ()) op = ir::Opcode::ICmpEQ;
+      else if (ctx->NE()) op = ir::Opcode::ICmpNE;
+      return EvalCmpImpl(*ctx->exp(0), *ctx->exp(1), op);
    }

    std::any visitAndExp(SysYParser::AndExpContext* ctx) override {
@@ -432,53 +415,165 @@ std::any IRGenImpl::visitUnarySubExp(SysYParser::UnarySubExpContext* ctx) {
    return static_cast<ir::Value*>(builder_.CreateBinary(ir::Opcode::int_opcode, lhs, rhs, module_.GetContext().NextTemp())); \
  }

-DEFINE_ARITH_VISITOR(Add, Add, FAdd)
-DEFINE_ARITH_VISITOR(Sub, Sub, FSub)
-DEFINE_ARITH_VISITOR(Mul, Mul, FMul)
-DEFINE_ARITH_VISITOR(Div, Div, FDiv)
+std::any IRGenImpl::visitMulDivModExp(SysYParser::MulDivModExpContext* ctx) {
+  ir::Value* lhs = EvalExpr(*ctx->exp(0));
+  ir::Value* rhs = EvalExpr(*ctx->exp(1));
  
-std::any IRGenImpl::visitModExp(SysYParser::ModExpContext* ctx) {
-  ir::Value* lhs = CastValue(*this, builder_, module_, EvalExpr(*ctx->exp(0)),
-                             ir::Type::GetInt32Type());
-  ir::Value* rhs = CastValue(*this, builder_, module_, EvalExpr(*ctx->exp(1)),
-                             ir::Type::GetInt32Type());
+  bool is_mul = ctx->MUL() != nullptr;
+  bool is_div = ctx->DIV() != nullptr;
+  bool is_mod = ctx->MOD() != nullptr;
+
+  if (is_mod) {
+    lhs = CastValue(*this, builder_, module_, lhs, ir::Type::GetInt32Type());
+    rhs = CastValue(*this, builder_, module_, rhs, ir::Type::GetInt32Type());
    if (auto* lconst = dynamic_cast<ir::ConstantValue*>(lhs)) {
      if (auto* rconst = dynamic_cast<ir::ConstantValue*>(rhs)) {
        const int rv = AsInt(rconst);
-      return static_cast<ir::Value*>(
-          module_.GetContext().GetConstInt(rv == 0 ? 0 : AsInt(lconst) % rv));
+        return static_cast<ir::Value*>(module_.GetContext().GetConstInt(rv == 0 ? 0 : AsInt(lconst) % rv));
      }
    }
-  return static_cast<ir::Value*>(
-      builder_.CreateMod(lhs, rhs, module_.GetContext().NextTemp()));
+    return static_cast<ir::Value*>(builder_.CreateMod(lhs, rhs, module_.GetContext().NextTemp()));
+  }
+
+  const auto common_ty = CommonArithType(lhs, rhs);
+  lhs = CastValue(*this, builder_, module_, lhs, common_ty);
+  rhs = CastValue(*this, builder_, module_, rhs, common_ty);
+
+  if (auto* lconst = dynamic_cast<ir::ConstantValue*>(lhs)) {
+    if (auto* rconst = dynamic_cast<ir::ConstantValue*>(rhs)) {
+      if (common_ty->IsFloat()) {
+        const float lv = AsFloat(lconst);
+        const float rv = AsFloat(rconst);
+        if (is_mul) return static_cast<ir::Value*>(module_.GetContext().GetConstFloat(lv * rv));
+        else return static_cast<ir::Value*>(module_.GetContext().GetConstFloat(rv == 0.0f ? 0.0f : lv / rv));
+      }
+      const int lv = AsInt(lconst);
+      const int rv = AsInt(rconst);
+      if (is_mul) return static_cast<ir::Value*>(module_.GetContext().GetConstInt(lv * rv));
+      else return static_cast<ir::Value*>(module_.GetContext().GetConstInt(rv == 0 ? 0 : lv / rv));
+    }
+  }
+
+  if (common_ty->IsFloat()) {
+    if (is_mul) return static_cast<ir::Value*>(builder_.CreateFMul(lhs, rhs, module_.GetContext().NextTemp()));
+    else return static_cast<ir::Value*>(builder_.CreateFDiv(lhs, rhs, module_.GetContext().NextTemp()));
+  }
+  if (is_mul) return static_cast<ir::Value*>(builder_.CreateBinary(ir::Opcode::Mul, lhs, rhs, module_.GetContext().NextTemp()));
+  else return static_cast<ir::Value*>(builder_.CreateBinary(ir::Opcode::Div, lhs, rhs, module_.GetContext().NextTemp()));
 }

-#define DEFINE_CMP_VISITOR(name, int_opcode, float_opcode, cmp_op)                   \
-  std::any IRGenImpl::visit##name##Exp(SysYParser::name##ExpContext* ctx) {         \
-    ir::Value* lhs = EvalExpr(*ctx->exp(0));                                         \
-    ir::Value* rhs = EvalExpr(*ctx->exp(1));                                         \
-    const auto common_ty = CommonArithType(lhs, rhs);                                \
-    lhs = CastValue(*this, builder_, module_, lhs, common_ty);                       \
-    rhs = CastValue(*this, builder_, module_, rhs, common_ty);                       \
-    if (auto* lconst = dynamic_cast<ir::ConstantValue*>(lhs)) {                      \
-      if (auto* rconst = dynamic_cast<ir::ConstantValue*>(rhs)) {                    \
-        const bool result = common_ty->IsFloat() ? (AsFloat(lconst) cmp_op AsFloat(rconst)) \
-                                                 : (AsInt(lconst) cmp_op AsInt(rconst)); \
-        return static_cast<ir::Value*>(module_.GetContext().GetConstInt(result ? 1 : 0)); \
-      }                                                                              \
-    }                                                                                \
-    if (common_ty->IsFloat()) {                                                      \
-      return static_cast<ir::Value*>(builder_.CreateFCmp(ir::Opcode::float_opcode, lhs, rhs, module_.GetContext().NextTemp())); \
-    }                                                                                \
-    return static_cast<ir::Value*>(builder_.CreateICmp(ir::Opcode::int_opcode, lhs, rhs, module_.GetContext().NextTemp())); \
+std::any IRGenImpl::visitAddSubExp(SysYParser::AddSubExpContext* ctx) {
+  ir::Value* lhs = EvalExpr(*ctx->exp(0));
+  ir::Value* rhs = EvalExpr(*ctx->exp(1));
+  const auto common_ty = CommonArithType(lhs, rhs);
+  lhs = CastValue(*this, builder_, module_, lhs, common_ty);
+  rhs = CastValue(*this, builder_, module_, rhs, common_ty);
+
+  bool is_sub = ctx->SUB() != nullptr;
+
+  if (auto* lconst = dynamic_cast<ir::ConstantValue*>(lhs)) {
+    if (auto* rconst = dynamic_cast<ir::ConstantValue*>(rhs)) {
+      if (common_ty->IsFloat()) {
+        const float lv = AsFloat(lconst);
+        const float rv = AsFloat(rconst);
+        return static_cast<ir::Value*>(module_.GetContext().GetConstFloat(is_sub ? lv - rv : lv + rv));
+      }
+      const int lv = AsInt(lconst);
+      const int rv = AsInt(rconst);
+      return static_cast<ir::Value*>(module_.GetContext().GetConstInt(is_sub ? lv - rv : lv + rv));
+    }
  }

-DEFINE_CMP_VISITOR(Lt, ICmpLT, FCmpLT, <)
-DEFINE_CMP_VISITOR(Le, ICmpLE, FCmpLE, <=)
-DEFINE_CMP_VISITOR(Gt, ICmpGT, FCmpGT, >)
-DEFINE_CMP_VISITOR(Ge, ICmpGE, FCmpGE, >=)
-DEFINE_CMP_VISITOR(Eq, ICmpEQ, FCmpEQ, ==)
-DEFINE_CMP_VISITOR(Ne, ICmpNE, FCmpNE, !=)
+  if (common_ty->IsFloat()) {
+    if (is_sub) return static_cast<ir::Value*>(builder_.CreateFSub(lhs, rhs, module_.GetContext().NextTemp()));
+    else return static_cast<ir::Value*>(builder_.CreateFAdd(lhs, rhs, module_.GetContext().NextTemp()));
+  }
+  if (is_sub) return static_cast<ir::Value*>(builder_.CreateBinary(ir::Opcode::Sub, lhs, rhs, module_.GetContext().NextTemp()));
+  else return static_cast<ir::Value*>(builder_.CreateBinary(ir::Opcode::Add, lhs, rhs, module_.GetContext().NextTemp()));
+}
+
+std::any IRGenImpl::visitRelExp(SysYParser::RelExpContext* ctx) {
+  ir::Value* lhs = EvalExpr(*ctx->exp(0));
+  ir::Value* rhs = EvalExpr(*ctx->exp(1));
+  const auto common_ty = CommonArithType(lhs, rhs);
+  lhs = CastValue(*this, builder_, module_, lhs, common_ty);
+  rhs = CastValue(*this, builder_, module_, rhs, common_ty);
+
+  ir::Opcode int_op = ir::Opcode::ICmpLT;
+  ir::Opcode float_op = ir::Opcode::FCmpLT;
+  bool is_lt = ctx->LT() != nullptr;
+  bool is_le = ctx->LE() != nullptr;
+  bool is_gt = ctx->GT() != nullptr;
+  bool is_ge = ctx->GE() != nullptr;
+
+  if (is_lt) { int_op = ir::Opcode::ICmpLT; float_op = ir::Opcode::FCmpLT; }
+  else if (is_le) { int_op = ir::Opcode::ICmpLE; float_op = ir::Opcode::FCmpLE; }
+  else if (is_gt) { int_op = ir::Opcode::ICmpGT; float_op = ir::Opcode::FCmpGT; }
+  else if (is_ge) { int_op = ir::Opcode::ICmpGE; float_op = ir::Opcode::FCmpGE; }
+
+  if (auto* lconst = dynamic_cast<ir::ConstantValue*>(lhs)) {
+    if (auto* rconst = dynamic_cast<ir::ConstantValue*>(rhs)) {
+      bool result = false;
+      if (common_ty->IsFloat()) {
+        float lv = AsFloat(lconst);
+        float rv = AsFloat(rconst);
+        if (is_lt) result = lv < rv;
+        else if (is_le) result = lv <= rv;
+        else if (is_gt) result = lv > rv;
+        else if (is_ge) result = lv >= rv;
+      } else {
+        int lv = AsInt(lconst);
+        int rv = AsInt(rconst);
+        if (is_lt) result = lv < rv;
+        else if (is_le) result = lv <= rv;
+        else if (is_gt) result = lv > rv;
+        else if (is_ge) result = lv >= rv;
+      }
+      return static_cast<ir::Value*>(module_.GetContext().GetConstInt(result ? 1 : 0));
+    }
+  }
+
+  if (common_ty->IsFloat()) {
+    return static_cast<ir::Value*>(builder_.CreateFCmp(float_op, lhs, rhs, module_.GetContext().NextTemp()));
+  }
+  return static_cast<ir::Value*>(builder_.CreateICmp(int_op, lhs, rhs, module_.GetContext().NextTemp()));
+}
+
+std::any IRGenImpl::visitEqNeExp(SysYParser::EqNeExpContext* ctx) {
+  ir::Value* lhs = EvalExpr(*ctx->exp(0));
+  ir::Value* rhs = EvalExpr(*ctx->exp(1));
+  const auto common_ty = CommonArithType(lhs, rhs);
+  lhs = CastValue(*this, builder_, module_, lhs, common_ty);
+  rhs = CastValue(*this, builder_, module_, rhs, common_ty);
+
+  ir::Opcode int_op = ir::Opcode::ICmpEQ;
+  ir::Opcode float_op = ir::Opcode::FCmpEQ;
+  bool is_eq = ctx->EQ() != nullptr;
+
+  if (is_eq) { int_op = ir::Opcode::ICmpEQ; float_op = ir::Opcode::FCmpEQ; }
+  else { int_op = ir::Opcode::ICmpNE; float_op = ir::Opcode::FCmpNE; }
+
+  if (auto* lconst = dynamic_cast<ir::ConstantValue*>(lhs)) {
+    if (auto* rconst = dynamic_cast<ir::ConstantValue*>(rhs)) {
+      bool result = false;
+      if (common_ty->IsFloat()) {
+        float lv = AsFloat(lconst);
+        float rv = AsFloat(rconst);
+        result = is_eq ? (lv == rv) : (lv != rv);
+      } else {
+        int lv = AsInt(lconst);
+        int rv = AsInt(rconst);
+        result = is_eq ? (lv == rv) : (lv != rv);
+      }
+      return static_cast<ir::Value*>(module_.GetContext().GetConstInt(result ? 1 : 0));
+    }
+  }
+
+  if (common_ty->IsFloat()) {
+    return static_cast<ir::Value*>(builder_.CreateFCmp(float_op, lhs, rhs, module_.GetContext().NextTemp()));
+  }
+  return static_cast<ir::Value*>(builder_.CreateICmp(int_op, lhs, rhs, module_.GetContext().NextTemp()));
+}

 std::any IRGenImpl::visitAndExp(SysYParser::AndExpContext* ctx) {
  if (!builder_.GetInsertBlock()) {
@@ -611,7 +706,8 @@ ir::Value* IRGenImpl::DecayArrayPtr(SysYParser::LValueContext* ctx) {
  const auto base_ty = GetDefType(def);

  if (dynamic_cast<SysYParser::FuncFParamContext*>(def)) {
-    if (ctx->exp().empty()) return base_ptr;
+    ir::Value* loaded_base = builder_.CreateLoad(base_ptr, module_.GetContext().NextTemp());
+    if (ctx->exp().empty()) return loaded_base;

    ir::Value* offset = CastValue(*this, builder_, module_, EvalExpr(*ctx->exp(0)),
                                  ir::Type::GetInt32Type());
@@ -628,7 +724,7 @@ ir::Value* IRGenImpl::DecayArrayPtr(SysYParser::LValueContext* ctx) {
          module_.GetContext().NextTemp());
      cur_ty = arr_ty->GetElementType();
    }
-    return builder_.CreateGEP(ScalarPointerType(cur_ty), base_ptr, {offset},
+    return builder_.CreateGEP(ScalarPointerType(cur_ty), loaded_base, {offset},
                              module_.GetContext().NextTemp());
  }

--- a/src/mir/AsmPrinter.cpp
+++ b/src/mir/AsmPrinter.cpp
@@ -25,7 +25,7 @@ bool IsFloatReg(PhysReg reg) {
 }

 void PrintStackAccess(std::ostream& os, const char* mnemonic, PhysReg reg,
-                      int offset) {
+                      int offset, int frame_size) {
  bool is_float = IsFloatReg(reg);
  const char* ldr_cmd = is_float ? "ldr" : "ldr";
  const char* str_cmd = is_float ? "str" : "str";
@@ -38,9 +38,23 @@ void PrintStackAccess(std::ostream& os, const char* mnemonic, PhysReg reg,
      os << "  " << mnemonic << " " << PhysRegName(reg) << ", [x29, #" << offset << "]\n";
    }
  } else {
-    os << "  mov x10, #" << offset << "\n";
+    int sp_offset = frame_size + offset;
+    int access_size = 4;
+    if ((reg >= PhysReg::X0 && reg <= PhysReg::X28) ||
+        reg == PhysReg::X29 || reg == PhysReg::X30 ||
+        reg == PhysReg::SP) {
+      access_size = 8;
+    }
+    int max_offset = access_size == 8 ? 32760 : 16380;
+    if (sp_offset >= 0 && sp_offset <= max_offset &&
+        sp_offset % access_size == 0) {
+      os << "  " << base_mnemonic << " " << PhysRegName(reg)
+         << ", [sp, #" << sp_offset << "]\n";
+    } else {
+      os << "  ldr x10, =" << offset << "\n";
      os << "  " << base_mnemonic << " " << PhysRegName(reg) << ", [x29, x10]\n";
    }
+  }
 }

 std::string GetBlockLabel(const std::string& func_name, const std::string& block_name) {
@@ -80,12 +94,24 @@ void PrintAsm(const MachineFunction& function, std::ostream& os) {
          os << "  stp x29, x30, [sp, #-16]!\n";
          os << "  mov x29, sp\n";
          if (function.GetFrameSize() > 0) {
-            os << "  sub sp, sp, #" << function.GetFrameSize() << "\n";
+            int size = function.GetFrameSize();
+            if (size <= 4095) {
+              os << "  sub sp, sp, #" << size << "\n";
+            } else {
+              os << "  ldr x9, =" << size << "\n";
+              os << "  sub sp, sp, x9\n";
+            }
          }
          break;
        case Opcode::Epilogue:
          if (function.GetFrameSize() > 0) {
-            os << "  add sp, sp, #" << function.GetFrameSize() << "\n";
+            int size = function.GetFrameSize();
+            if (size <= 4095) {
+              os << "  add sp, sp, #" << size << "\n";
+            } else {
+              os << "  ldr x9, =" << size << "\n";
+              os << "  add sp, sp, x9\n";
+            }
          }
          os << "  ldp x29, x30, [sp], #16\n";
          break;
@@ -102,18 +128,25 @@ void PrintAsm(const MachineFunction& function, std::ostream& os) {
            os << "  adrp x8, " << flabel << "\n";
            os << "  ldr " << PhysRegName(dst) << ", [x8, :lo12:" << flabel << "]\n";
          } else {
-            os << "  mov " << PhysRegName(dst) << ", #" << ops.at(1).GetImm() << "\n";
+            int imm = ops.at(1).GetImm();
+            if (imm >= 0 && imm <= 65535) {
+              os << "  mov " << PhysRegName(dst) << ", #" << imm << "\n";
+            } else {
+              os << "  ldr " << PhysRegName(dst) << ", =" << imm << "\n";
+            }
          }
          break;
        }
        case Opcode::LoadStack: {
          const auto& slot = GetFrameSlot(function, ops.at(1));
-          PrintStackAccess(os, "ldur", ops.at(0).GetReg(), slot.offset);
+          PrintStackAccess(os, "ldur", ops.at(0).GetReg(), slot.offset,
+                           function.GetFrameSize());
          break;
        }
        case Opcode::StoreStack: {
          const auto& slot = GetFrameSlot(function, ops.at(1));
-          PrintStackAccess(os, "stur", ops.at(0).GetReg(), slot.offset);
+          PrintStackAccess(os, "stur", ops.at(0).GetReg(), slot.offset,
+                           function.GetFrameSize());
          break;
        }
        case Opcode::AddRR:
@@ -201,18 +234,43 @@ void PrintAsm(const MachineFunction& function, std::ostream& os) {
             << ops.at(1).GetGlobalName() << "\n";
          break;
        case Opcode::AddRegImm: {
-          os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", ";
+          PhysReg dst = ops.at(0).GetReg();
+          PhysReg src = ops.at(1).GetReg();
          if (ops.at(2).GetKind() == Operand::Kind::FrameIndex) {
            const auto& slot = function.GetFrameSlot(ops.at(2).GetFrameIndex());
-            os << "#" << slot.offset << "\n";
-          } else if (ops.at(2).GetKind() == Operand::Kind::Global) {
-            os << ":lo12:" << ops.at(2).GetGlobalName() << "\n";
+            int offset = slot.offset;
+            if (offset >= -4095 && offset <= 4095) {
+              if (offset >= 0) {
+                os << "  add " << PhysRegName(dst) << ", " << PhysRegName(src) << ", #" << offset << "\n";
              } else {
-            os << "#" << ops.at(2).GetImm() << "\n";
+                os << "  sub " << PhysRegName(dst) << ", " << PhysRegName(src) << ", #" << (-offset) << "\n";
+              }
+            } else {
+              os << "  ldr x9, =" << offset << "\n";
+              os << "  add " << PhysRegName(dst) << ", " << PhysRegName(src) << ", x9\n";
+            }
+          } else if (ops.at(2).GetKind() == Operand::Kind::Global) {
+            os << "  add " << PhysRegName(dst) << ", " << PhysRegName(src) << ", :lo12:" << ops.at(2).GetGlobalName() << "\n";
+          } else {
+            int imm = ops.at(2).GetImm();
+            if (imm >= -4095 && imm <= 4095) {
+              if (imm >= 0) {
+                os << "  add " << PhysRegName(dst) << ", " << PhysRegName(src) << ", #" << imm << "\n";
+              } else {
+                os << "  sub " << PhysRegName(dst) << ", " << PhysRegName(src) << ", #" << (-imm) << "\n";
+              }
+            } else {
+              os << "  ldr x9, =" << imm << "\n";
+              os << "  add " << PhysRegName(dst) << ", " << PhysRegName(src) << ", x9\n";
+            }
          }
          break;
        }
+        case Opcode::LslImm:
+          os << "  lsl " << PhysRegName(ops.at(0).GetReg()) << ", "
+             << PhysRegName(ops.at(1).GetReg()) << ", #"
+             << ops.at(2).GetImm() << "\n";
+          break;
        case Opcode::LdrRegReg: {
          PhysReg reg = ops.at(0).GetReg();
          const char* ldr_cmd = IsFloatReg(reg) ? "ldr" : "ldr";
--- a/src/mir/FrameLowering.cpp
+++ b/src/mir/FrameLowering.cpp
@@ -33,6 +33,21 @@ void RunFrameLowering(MachineFunction& function) {
  auto& blocks = function.GetBlocks();
  if (blocks.empty()) return;

+  bool has_call = false;
+  for (const auto& block : blocks) {
+    for (const auto& inst : block.GetInstructions()) {
+      if (inst.GetOpcode() == Opcode::Call) {
+        has_call = true;
+        break;
+      }
+    }
+    if (has_call) break;
+  }
+
+  if (function.GetFrameSize() == 0 && !has_call) {
+    return;
+  }
+
  // Insert Prologue at the start of the first block
  auto& entry_insts = blocks.front().GetInstructions();
  entry_insts.insert(entry_insts.begin(), MachineInstr(Opcode::Prologue));
--- a/src/mir/Lowering.cpp
+++ b/src/mir/Lowering.cpp
@@ -2,6 +2,7 @@

 #include <stdexcept>
 #include <unordered_map>
+#include <unordered_set>
 #include <vector>
 #include <cstring>

@@ -28,34 +29,101 @@ uint32_t GetTypeSize(const ir::Type* type) {
  return 4;
 }

-uint32_t GetAllocaSize(const ir::Instruction& inst) {
-  auto type = inst.GetType();
-  if (type->IsPtrInt32() || type->IsPtrFloat()) {
-    // Check if any StoreInst in the parent function stores a pointer to this alloca
-    auto* parent_bb = inst.GetParent();
+std::unordered_set<const ir::Value*> IdentifyPointerValues(const ir::Function& function) {
+  std::unordered_set<const ir::Value*> pointers;
+
+  // 1. Arguments that are pointers
+  for (const auto& arg : function.GetArguments()) {
+    if (arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat()) {
+      pointers.insert(arg.get());
+    }
+  }
+
+  // 2. Alloca instructions that store a pointer argument
+  for (const auto& bbPtr : function.GetBlocks()) {
+    for (const auto& instPtr : bbPtr->GetInstructions()) {
+      const auto* inst = instPtr.get();
+      if (inst->GetOpcode() == ir::Opcode::Alloca) {
+        bool stores_ptr = false;
+        auto* parent_bb = inst->GetParent();
        if (parent_bb) {
          auto* parent_func = parent_bb->GetParent();
          if (parent_func) {
-        for (const auto& bbPtr : parent_func->GetBlocks()) {
-          for (const auto& other_inst : bbPtr->GetInstructions()) {
+            for (const auto& other_bb : parent_func->GetBlocks()) {
+              for (const auto& other_inst : other_bb->GetInstructions()) {
                if (other_inst->GetOpcode() == ir::Opcode::Store) {
                  auto* store = static_cast<const ir::StoreInst*>(other_inst.get());
-              if (store->GetPtr() == &inst) {
-                auto val_ty = store->GetValue()->GetType();
-                if (val_ty->IsPtrInt32() || val_ty->IsPtrFloat()) {
+                  if (store->GetPtr() == inst) {
+                    auto* val = store->GetValue();
+                    if (val->GetType()->IsPtrInt32() || val->GetType()->IsPtrFloat() || pointers.find(val) != pointers.end()) {
+                      stores_ptr = true;
+                      break;
+                    }
+                  }
+                }
+              }
+              if (stores_ptr) break;
+            }
+          }
+        }
+        if (stores_ptr) {
+          pointers.insert(inst);
+        }
+      }
+    }
+  }
+
+  // 3. GEP instructions
+  for (const auto& bbPtr : function.GetBlocks()) {
+    for (const auto& instPtr : bbPtr->GetInstructions()) {
+      const auto* inst = instPtr.get();
+      if (inst->GetOpcode() == ir::Opcode::GEP) {
+        pointers.insert(inst);
+      }
+    }
+  }
+
+  // 4. Load instructions that load from those pointer-storing allocas
+  for (const auto& bbPtr : function.GetBlocks()) {
+    for (const auto& instPtr : bbPtr->GetInstructions()) {
+      const auto* inst = instPtr.get();
+      if (inst->GetOpcode() == ir::Opcode::Load) {
+        auto* load = static_cast<const ir::LoadInst*>(inst);
+        if (pointers.find(load->GetPtr()) != pointers.end()) {
+          if (auto* alloca = dynamic_cast<const ir::Instruction*>(load->GetPtr())) {
+            if (alloca->GetOpcode() == ir::Opcode::Alloca) {
+              pointers.insert(inst);
+            }
+          }
+        }
+      }
+    }
+  }
+
+  return pointers;
+}
+
+uint32_t GetAllocaSize(const ir::Instruction& inst, const std::unordered_set<const ir::Value*>& pointers) {
+  auto type = inst.GetType();
+  if (pointers.find(&inst) != pointers.end()) {
    return 8; // Stores a 64-bit pointer
  }
-              }
-            }
-          }
-        }
-      }
-    }
-    return 4;
-  }
  return GetTypeSize(type.get());
 }

+bool IsPowerOfTwo(uint32_t value) {
+  return value != 0 && (value & (value - 1)) == 0;
+}
+
+int Log2(uint32_t value) {
+  int shift = 0;
+  while (value > 1) {
+    value >>= 1;
+    shift++;
+  }
+  return shift;
+}
+
 std::vector<uint32_t> GetGepStrides(const ir::GetElementPtrInst& gep) {
  std::vector<uint32_t> strides;
  auto curr_type = gep.GetPtr()->GetType();
@@ -127,10 +195,11 @@ void EmitValueToReg(const ir::Value* value, PhysReg target,
 }

 void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
-                      ValueSlotMap& slots, MachineBasicBlock& block) {
+                      ValueSlotMap& slots, MachineBasicBlock& block,
+                      const std::unordered_set<const ir::Value*>& pointers) {
  switch (inst.GetOpcode()) {
    case ir::Opcode::Alloca: {
-      slots.emplace(&inst, function.CreateFrameIndex(GetAllocaSize(inst)));
+      slots.emplace(&inst, function.CreateFrameIndex(GetAllocaSize(inst, pointers)));
      return;
    }
    case ir::Opcode::Store: {
@@ -140,8 +209,12 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
        if (alloca->GetOpcode() == ir::Opcode::Alloca) {
          auto it = slots.find(alloca);
          if (it != slots.end()) {
+            bool is_ptr = store.GetValue()->GetType()->IsPtrInt32() || 
+                          store.GetValue()->GetType()->IsPtrFloat() || 
+                          pointers.find(store.GetValue()) != pointers.end() ||
+                          store.GetValue()->IsGlobalValue();
            PhysReg val_reg = store.GetValue()->GetType()->IsFloat() ? PhysReg::S8 :
-                              (store.GetValue()->GetType()->IsPtrInt32() || store.GetValue()->GetType()->IsPtrFloat()) ? PhysReg::X8 : PhysReg::W8;
+                              is_ptr ? PhysReg::X8 : PhysReg::W8;
            EmitValueToReg(store.GetValue(), val_reg, slots, block);
            block.Append(Opcode::StoreStack, {Operand::Reg(val_reg), Operand::FrameIndex(it->second)});
            return;
@@ -150,8 +223,12 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
      }

      // Dynamic store
+      bool is_ptr = store.GetValue()->GetType()->IsPtrInt32() || 
+                    store.GetValue()->GetType()->IsPtrFloat() || 
+                    pointers.find(store.GetValue()) != pointers.end() ||
+                    store.GetValue()->IsGlobalValue();
      PhysReg val_reg = store.GetValue()->GetType()->IsFloat() ? PhysReg::S8 :
-                        (store.GetValue()->GetType()->IsPtrInt32() || store.GetValue()->GetType()->IsPtrFloat()) ? PhysReg::X8 : PhysReg::W8;
+                        is_ptr ? PhysReg::X8 : PhysReg::W8;
      EmitValueToReg(store.GetValue(), val_reg, slots, block);
      EmitAddressToReg(store.GetPtr(), PhysReg::X9, slots, block);
      block.Append(Opcode::StrRegReg, {Operand::Reg(val_reg), Operand::Reg(PhysReg::X9)});
@@ -159,7 +236,10 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
    }
    case ir::Opcode::Load: {
      auto& load = static_cast<const ir::LoadInst&>(inst);
-      int dst_slot = function.CreateFrameIndex(GetTypeSize(load.GetType().get()));
+      bool is_ptr = load.GetType()->IsPtrInt32() || 
+                    load.GetType()->IsPtrFloat() || 
+                    pointers.find(&inst) != pointers.end();
+      int dst_slot = function.CreateFrameIndex(is_ptr ? 8 : GetTypeSize(load.GetType().get()));
      slots.emplace(&inst, dst_slot);

      if (auto* alloca = dynamic_cast<const ir::Instruction*>(load.GetPtr())) {
@@ -167,7 +247,7 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
          auto it = slots.find(alloca);
          if (it != slots.end()) {
            PhysReg val_reg = load.GetType()->IsFloat() ? PhysReg::S8 :
-                              (load.GetType()->IsPtrInt32() || load.GetType()->IsPtrFloat()) ? PhysReg::X8 : PhysReg::W8;
+                              is_ptr ? PhysReg::X8 : PhysReg::W8;
            block.Append(Opcode::LoadStack, {Operand::Reg(val_reg), Operand::FrameIndex(it->second)});
            block.Append(Opcode::StoreStack, {Operand::Reg(val_reg), Operand::FrameIndex(dst_slot)});
            return;
@@ -177,7 +257,7 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,

      // Dynamic load
      PhysReg val_reg = load.GetType()->IsFloat() ? PhysReg::S8 :
-                        (load.GetType()->IsPtrInt32() || load.GetType()->IsPtrFloat()) ? PhysReg::X8 : PhysReg::W8;
+                        is_ptr ? PhysReg::X8 : PhysReg::W8;
      EmitAddressToReg(load.GetPtr(), PhysReg::X9, slots, block);
      block.Append(Opcode::LdrRegReg, {Operand::Reg(val_reg), Operand::Reg(PhysReg::X9)});
      block.Append(Opcode::StoreStack, {Operand::Reg(val_reg), Operand::FrameIndex(dst_slot)});
@@ -192,6 +272,61 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
      int dst_slot = function.CreateFrameIndex(4);
      slots.emplace(&inst, dst_slot);

+      if (inst.GetOpcode() == ir::Opcode::Add) {
+        const ir::Value* variable = nullptr;
+        int constant = 0;
+        if (auto* lhs_const = dynamic_cast<const ir::ConstantInt*>(bin.GetLhs())) {
+          variable = bin.GetRhs();
+          constant = lhs_const->GetValue();
+        } else if (auto* rhs_const = dynamic_cast<const ir::ConstantInt*>(bin.GetRhs())) {
+          variable = bin.GetLhs();
+          constant = rhs_const->GetValue();
+        }
+        if (variable && constant >= -4095 && constant <= 4095) {
+          EmitValueToReg(variable, PhysReg::W8, slots, block);
+          block.Append(Opcode::AddRegImm, {Operand::Reg(PhysReg::W8), Operand::Reg(PhysReg::W8), Operand::Imm(constant)});
+          block.Append(Opcode::StoreStack, {Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst_slot)});
+          return;
+        }
+      } else if (inst.GetOpcode() == ir::Opcode::Sub) {
+        if (auto* rhs_const = dynamic_cast<const ir::ConstantInt*>(bin.GetRhs())) {
+          int constant = rhs_const->GetValue();
+          if (constant >= -4095 && constant <= 4095) {
+            EmitValueToReg(bin.GetLhs(), PhysReg::W8, slots, block);
+            block.Append(Opcode::AddRegImm, {Operand::Reg(PhysReg::W8), Operand::Reg(PhysReg::W8), Operand::Imm(-constant)});
+            block.Append(Opcode::StoreStack, {Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst_slot)});
+            return;
+          }
+        }
+      }
+
+      if (inst.GetOpcode() == ir::Opcode::Mul) {
+        const ir::Value* variable = nullptr;
+        int constant = 0;
+        if (auto* lhs_const = dynamic_cast<const ir::ConstantInt*>(bin.GetLhs())) {
+          variable = bin.GetRhs();
+          constant = lhs_const->GetValue();
+        } else if (auto* rhs_const = dynamic_cast<const ir::ConstantInt*>(bin.GetRhs())) {
+          variable = bin.GetLhs();
+          constant = rhs_const->GetValue();
+        }
+
+        if (variable && constant > 1) {
+          EmitValueToReg(variable, PhysReg::W8, slots, block);
+          if (IsPowerOfTwo(static_cast<uint32_t>(constant))) {
+            block.Append(Opcode::LslImm, {Operand::Reg(PhysReg::W8), Operand::Reg(PhysReg::W8), Operand::Imm(Log2(static_cast<uint32_t>(constant)))});
+            block.Append(Opcode::StoreStack, {Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst_slot)});
+            return;
+          }
+          if (IsPowerOfTwo(static_cast<uint32_t>(constant - 1))) {
+            block.Append(Opcode::LslImm, {Operand::Reg(PhysReg::W9), Operand::Reg(PhysReg::W8), Operand::Imm(Log2(static_cast<uint32_t>(constant - 1)))});
+            block.Append(Opcode::AddRR, {Operand::Reg(PhysReg::W8), Operand::Reg(PhysReg::W9), Operand::Reg(PhysReg::W8)});
+            block.Append(Opcode::StoreStack, {Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst_slot)});
+            return;
+          }
+        }
+      }
+
      EmitValueToReg(bin.GetLhs(), PhysReg::W8, slots, block);
      EmitValueToReg(bin.GetRhs(), PhysReg::W9, slots, block);

@@ -342,8 +477,12 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
              auto slot_it = slots.find(phi);
              if (slot_it != slots.end()) {
                int phi_slot = slot_it->second;
+                bool is_ptr = phi->GetType()->IsPtrInt32() || 
+                              phi->GetType()->IsPtrFloat() || 
+                              pointers.find(phi) != pointers.end() ||
+                              (incoming_val && (pointers.find(incoming_val) != pointers.end() || incoming_val->IsGlobalValue()));
                PhysReg val_reg = phi->GetType()->IsFloat() ? PhysReg::S8 :
-                                  (phi->GetType()->IsPtrInt32() || phi->GetType()->IsPtrFloat()) ? PhysReg::X8 : PhysReg::W8;
+                                  is_ptr ? PhysReg::X8 : PhysReg::W8;
                EmitValueToReg(incoming_val, val_reg, slots, block);
                block.Append(Opcode::StoreStack, {Operand::Reg(val_reg), Operand::FrameIndex(phi_slot)});
              }
@@ -372,7 +511,12 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
    case ir::Opcode::Ret: {
      auto& ret = static_cast<const ir::ReturnInst&>(inst);
      if (ret.GetValue()) {
-        PhysReg ret_reg = ret.GetValue()->GetType()->IsFloat() ? PhysReg::S0 : PhysReg::W0;
+        bool is_ptr = ret.GetValue()->GetType()->IsPtrInt32() || 
+                      ret.GetValue()->GetType()->IsPtrFloat() || 
+                      pointers.find(ret.GetValue()) != pointers.end() ||
+                      ret.GetValue()->IsGlobalValue();
+        PhysReg ret_reg = ret.GetValue()->GetType()->IsFloat() ? PhysReg::S0 :
+                          is_ptr ? PhysReg::X0 : PhysReg::W0;
        EmitValueToReg(ret.GetValue(), ret_reg, slots, block);
      }
      block.Append(Opcode::Ret);
@@ -380,9 +524,12 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
    }
    case ir::Opcode::Call: {
      auto& call = static_cast<const ir::CallInst&>(inst);
+      bool is_ret_ptr = call.GetType()->IsPtrInt32() || 
+                        call.GetType()->IsPtrFloat() || 
+                        pointers.find(&inst) != pointers.end();
      int dst_slot = -1;
      if (!call.GetType()->IsVoid()) {
-        dst_slot = function.CreateFrameIndex(GetTypeSize(call.GetType().get()));
+        dst_slot = function.CreateFrameIndex(is_ret_ptr ? 8 : GetTypeSize(call.GetType().get()));
        slots.emplace(&inst, dst_slot);
      }

@@ -395,7 +542,11 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
          EmitValueToReg(arg, reg, slots, block);
          float_idx++;
        } else {
-          PhysReg reg = (arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat())
+          bool is_arg_ptr = arg->GetType()->IsPtrInt32() || 
+                            arg->GetType()->IsPtrFloat() || 
+                            pointers.find(arg) != pointers.end() ||
+                            arg->IsGlobalValue();
+          PhysReg reg = is_arg_ptr
                            ? static_cast<PhysReg>(static_cast<int>(PhysReg::X0) + int_idx)
                            : static_cast<PhysReg>(static_cast<int>(PhysReg::W0) + int_idx);
          EmitValueToReg(arg, reg, slots, block);
@@ -409,7 +560,7 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
        if (call.GetType()->IsFloat()) {
          block.Append(Opcode::StoreStack, {Operand::Reg(PhysReg::S0), Operand::FrameIndex(dst_slot)});
        } else {
-          PhysReg ret_reg = (call.GetType()->IsPtrInt32() || call.GetType()->IsPtrFloat()) ? PhysReg::X0 : PhysReg::W0;
+          PhysReg ret_reg = is_ret_ptr ? PhysReg::X0 : PhysReg::W0;
          block.Append(Opcode::StoreStack, {Operand::Reg(ret_reg), Operand::FrameIndex(dst_slot)});
        }
      }
@@ -438,21 +589,29 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
        auto* idx = gep.GetOperand(i);
        uint32_t stride = strides.at(i - 1);
        
-        // Skip if offset index is constant 0
        if (auto* ci = dynamic_cast<const ir::ConstantInt*>(idx)) {
-          if (ci->GetValue() == 0) {
-            continue;
+          int64_t offset = static_cast<int64_t>(ci->GetValue()) * stride;
+          if (offset != 0) {
+            block.Append(Opcode::AddRegImm, {Operand::Reg(PhysReg::X8), Operand::Reg(PhysReg::X8), Operand::Imm(offset)});
          }
+          continue;
        }

        EmitValueToReg(idx, PhysReg::W9, slots, block);
-        if (stride > 1) {
+        bool shifted = false;
+        if (stride > 1 && IsPowerOfTwo(stride)) {
+          block.Append(Opcode::ZExt, {Operand::Reg(PhysReg::X9), Operand::Reg(PhysReg::W9)});
+          block.Append(Opcode::LslImm, {Operand::Reg(PhysReg::X9), Operand::Reg(PhysReg::X9), Operand::Imm(Log2(stride))});
+          shifted = true;
+        } else if (stride > 1) {
          block.Append(Opcode::MovImm, {Operand::Reg(PhysReg::W10), Operand::Imm(stride)});
          block.Append(Opcode::MulRR, {Operand::Reg(PhysReg::W9), Operand::Reg(PhysReg::W9), Operand::Reg(PhysReg::W10)});
        }

        // Extend W9 to X9 and add to base address X8
+        if (!shifted) {
          block.Append(Opcode::ZExt, {Operand::Reg(PhysReg::X9), Operand::Reg(PhysReg::W9)});
+        }
        block.Append(Opcode::AddRR, {Operand::Reg(PhysReg::X8), Operand::Reg(PhysReg::X8), Operand::Reg(PhysReg::X9)});
      }

@@ -477,6 +636,7 @@ std::vector<std::unique_ptr<MachineFunction>> LowerToMIR(const ir::Module& modul

    auto machine_func = std::make_unique<MachineFunction>(func.GetName());
    ValueSlotMap slots;
+    auto pointers = IdentifyPointerValues(func);

    // First, create all basic blocks in MachineFunction
    std::unordered_map<const ir::BasicBlock*, MachineBasicBlock*> bb_map;
@@ -490,7 +650,10 @@ std::vector<std::unique_ptr<MachineFunction>> LowerToMIR(const ir::Module& modul
    for (const auto& bbPtr : func.GetBlocks()) {
      for (const auto& inst : bbPtr->GetInstructions()) {
        if (inst->GetOpcode() == ir::Opcode::Phi) {
-          int slot = machine_func->CreateFrameIndex(GetTypeSize(inst->GetType().get()));
+          bool is_phi_ptr = inst->GetType()->IsPtrInt32() || 
+                            inst->GetType()->IsPtrFloat() || 
+                            pointers.find(inst.get()) != pointers.end();
+          int slot = machine_func->CreateFrameIndex(is_phi_ptr ? 8 : GetTypeSize(inst->GetType().get()));
          slots.emplace(inst.get(), slot);
        }
      }
@@ -503,7 +666,10 @@ std::vector<std::unique_ptr<MachineFunction>> LowerToMIR(const ir::Module& modul
    int int_idx = 0;
    int float_idx = 0;
    for (const auto& arg : args) {
-      int slot = machine_func->CreateFrameIndex(GetTypeSize(arg->GetType().get()));
+      bool is_arg_ptr = arg->GetType()->IsPtrInt32() || 
+                        arg->GetType()->IsPtrFloat() || 
+                        pointers.find(arg.get()) != pointers.end();
+      int slot = machine_func->CreateFrameIndex(is_arg_ptr ? 8 : GetTypeSize(arg->GetType().get()));
      slots.emplace(arg.get(), slot);

      if (arg->GetType()->IsFloat()) {
@@ -511,7 +677,7 @@ std::vector<std::unique_ptr<MachineFunction>> LowerToMIR(const ir::Module& modul
        entry_block.Append(Opcode::StoreStack, {Operand::Reg(reg), Operand::FrameIndex(slot)});
        float_idx++;
      } else {
-        PhysReg reg = (arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat())
+        PhysReg reg = is_arg_ptr
                          ? static_cast<PhysReg>(static_cast<int>(PhysReg::X0) + int_idx)
                          : static_cast<PhysReg>(static_cast<int>(PhysReg::W0) + int_idx);
        entry_block.Append(Opcode::StoreStack, {Operand::Reg(reg), Operand::FrameIndex(slot)});
@@ -523,7 +689,7 @@ std::vector<std::unique_ptr<MachineFunction>> LowerToMIR(const ir::Module& modul
    for (const auto& bbPtr : func.GetBlocks()) {
      auto& mbb = *bb_map.at(bbPtr.get());
      for (const auto& inst : bbPtr->GetInstructions()) {
-        LowerInstruction(*inst, *machine_func, slots, mbb);
+        LowerInstruction(*inst, *machine_func, slots, mbb, pointers);
      }
    }

--- a/src/mir/passes/Peephole.cpp
+++ b/src/mir/passes/Peephole.cpp
@@ -1,11 +1,16 @@
 #include "mir/MIR.h"
 #include <unordered_map>
+#include <unordered_set>
 #include <vector>

 namespace mir {

 namespace {

+int AlignTo(int value, int align) {
+  return ((value + align - 1) / align) * align;
+}
+
 PhysReg NormalizeReg(PhysReg reg) {
  int r = static_cast<int>(reg);
  // Map 64-bit X0-X28 registers to 32-bit W0-W28 registers to handle aliasing
@@ -45,11 +50,85 @@ bool IsFloatReg(PhysReg reg) {
  return reg >= PhysReg::S0 && reg <= PhysReg::S15;
 }

+bool SameReg(const Operand& lhs, const Operand& rhs) {
+  return lhs.GetKind() == Operand::Kind::Reg &&
+         rhs.GetKind() == Operand::Kind::Reg &&
+         NormalizeReg(lhs.GetReg()) == NormalizeReg(rhs.GetReg());
+}
+
+bool IsZeroImm(const Operand& operand) {
+  return operand.GetKind() == Operand::Kind::Imm && operand.GetImm() == 0;
+}
+
+std::vector<MachineInstr> SimplifyCompareToBranch(
+    const std::vector<MachineInstr>& insts) {
+  std::vector<MachineInstr> simplified;
+
+  for (size_t i = 0; i < insts.size();) {
+    if (i + 4 < insts.size() &&
+        (insts[i].GetOpcode() == Opcode::CmpRR ||
+         insts[i].GetOpcode() == Opcode::FCmpRR) &&
+        insts[i + 1].GetOpcode() == Opcode::Cset &&
+        insts[i + 2].GetOpcode() == Opcode::MovImm &&
+        insts[i + 3].GetOpcode() == Opcode::CmpRR &&
+        insts[i + 4].GetOpcode() == Opcode::BCond) {
+      const auto& cset_ops = insts[i + 1].GetOperands();
+      const auto& mov_ops = insts[i + 2].GetOperands();
+      const auto& cmp2_ops = insts[i + 3].GetOperands();
+      const auto& br_ops = insts[i + 4].GetOperands();
+
+      if (mov_ops.size() == 2 && cmp2_ops.size() == 2 && br_ops.size() == 2 &&
+          SameReg(cset_ops.at(0), cmp2_ops.at(0)) &&
+          SameReg(mov_ops.at(0), cmp2_ops.at(1)) &&
+          IsZeroImm(mov_ops.at(1)) &&
+          br_ops.at(0).GetKind() == Operand::Kind::Cond &&
+          br_ops.at(0).GetCondCode() == "ne") {
+        simplified.push_back(insts[i]);
+        simplified.emplace_back(Opcode::BCond,
+                                std::vector<Operand>{
+                                    Operand::Cond(cset_ops.at(1).GetCondCode()),
+                                    br_ops.at(1)});
+        i += 5;
+        continue;
+      }
+    }
+
+    simplified.push_back(insts[i]);
+    i++;
+  }
+
+  return simplified;
+}
+
+void CompactFrameSlots(MachineFunction& function) {
+  std::unordered_set<int> used_slots;
+  for (const auto& block : function.GetBlocks()) {
+    for (const auto& inst : block.GetInstructions()) {
+      for (const auto& opnd : inst.GetOperands()) {
+        if (opnd.GetKind() == Operand::Kind::FrameIndex) {
+          used_slots.insert(opnd.GetFrameIndex());
+        }
+      }
+    }
+  }
+
+  int cursor = 0;
+  for (const auto& slot : function.GetFrameSlots()) {
+    if (used_slots.find(slot.index) == used_slots.end()) {
+      continue;
+    }
+    cursor += slot.size;
+    function.GetFrameSlot(slot.index).offset = -cursor;
+  }
+  function.SetFrameSize(AlignTo(cursor, 16));
+}
+
 } // namespace

 void RunPeephole(MachineFunction& function) {
  for (auto& block : function.GetBlocks()) {
    auto& insts = block.GetInstructions();
+    insts = SimplifyCompareToBranch(insts);
    std::vector<MachineInstr> optimized;
    
    // Map from FrameIndex to the normalized physical register that currently holds its value
@@ -99,10 +178,14 @@ void RunPeephole(MachineFunction& function) {
        }
      }

-      // 3. Track stores
+      // 3. Track and optimize stores
      if (op == Opcode::StoreStack) {
        PhysReg src = NormalizeReg(ops.at(0).GetReg());
        int fi = ops.at(1).GetFrameIndex();
+        auto it = slot_to_reg.find(fi);
+        if (it != slot_to_reg.end() && NormalizeReg(it->second) == src) {
+          continue; // Delete redundant store
+        }
        slot_to_reg[fi] = src;
      }

@@ -145,6 +228,7 @@ void RunPeephole(MachineFunction& function) {
        case Opcode::MovReg:
        case Opcode::Adrp:
        case Opcode::AddRegImm:
+        case Opcode::LslImm:
        case Opcode::LdrRegReg:
        case Opcode::SIToFP:
        case Opcode::FPToSI:
@@ -180,6 +264,56 @@ void RunPeephole(MachineFunction& function) {
    
    insts = std::move(optimized);
  }
+  
+  // 5. Eliminate Dead Stack Slots (stores to slots that are never loaded or address-taken)
+  // Count loads and address-taken operations
+  std::unordered_map<int, int> load_count;
+  std::unordered_map<int, int> address_taken_count;
+
+  for (const auto& block : function.GetBlocks()) {
+    for (const auto& inst : block.GetInstructions()) {
+      Opcode op = inst.GetOpcode();
+      const auto& ops = inst.GetOperands();
+      
+      for (const auto& opnd : ops) {
+        if (opnd.GetKind() == Operand::Kind::FrameIndex) {
+          int fi = opnd.GetFrameIndex();
+          if (op == Opcode::LoadStack) {
+            load_count[fi]++;
+          } else if (op != Opcode::StoreStack) {
+            address_taken_count[fi]++;
+          }
+        }
+      }
+    }
+  }
+
+  // Identify dead slots
+  std::unordered_set<int> dead_slots;
+  for (size_t i = 0; i < function.GetFrameSlots().size(); ++i) {
+    int fi = static_cast<int>(i);
+    if (load_count[fi] == 0 && address_taken_count[fi] == 0) {
+      dead_slots.insert(fi);
+    }
+  }
+
+  // Remove StoreStack to dead slots
+  for (auto& block : function.GetBlocks()) {
+    auto& insts = block.GetInstructions();
+    std::vector<MachineInstr> optimized;
+    for (const auto& inst : insts) {
+      if (inst.GetOpcode() == Opcode::StoreStack) {
+        int fi = inst.GetOperands().at(1).GetFrameIndex();
+        if (dead_slots.find(fi) != dead_slots.end()) {
+          continue; // Delete this store
+        }
+      }
+      optimized.push_back(inst);
+    }
+    insts = std::move(optimized);
+  }
+
+  CompactFrameSlots(function);
 }

 } // namespace mir
--- a/src/sem/Sema.cpp
+++ b/src/sem/Sema.cpp
@@ -211,67 +211,25 @@ class SemaVisitor final : public SysYBaseVisitor {
    return ctx->exp()->accept(this);
  }

-  std::any visitMulExp(SysYParser::MulExpContext* ctx) override {
+  std::any visitMulDivModExp(SysYParser::MulDivModExpContext* ctx) override {
    ctx->exp(0)->accept(this);
    ctx->exp(1)->accept(this);
    return {};
  }

-  std::any visitDivExp(SysYParser::DivExpContext* ctx) override {
+  std::any visitAddSubExp(SysYParser::AddSubExpContext* ctx) override {
    ctx->exp(0)->accept(this);
    ctx->exp(1)->accept(this);
    return {};
  }

-  std::any visitModExp(SysYParser::ModExpContext* ctx) override {
+  std::any visitRelExp(SysYParser::RelExpContext* ctx) override {
    ctx->exp(0)->accept(this);
    ctx->exp(1)->accept(this);
    return {};
  }

-  std::any visitAddExp(SysYParser::AddExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitSubExp(SysYParser::SubExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitLtExp(SysYParser::LtExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitLeExp(SysYParser::LeExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitGtExp(SysYParser::GtExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitGeExp(SysYParser::GeExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitEqExp(SysYParser::EqExpContext* ctx) override {
-    ctx->exp(0)->accept(this);
-    ctx->exp(1)->accept(this);
-    return {};
-  }
-
-  std::any visitNeExp(SysYParser::NeExpContext* ctx) override {
+  std::any visitEqNeExp(SysYParser::EqNeExpContext* ctx) override {
    ctx->exp(0)->accept(this);
    ctx->exp(1)->accept(this);
    return {};
Author	SHA1	Message	Date
CGH0S7	a8b5d9c864	updated pptx and speech pdf	2026-06-30 11:51:38 +08:00
CGH0S7	d9d36e017f	updated scripts and pptx	2026-06-30 02:11:00 +08:00
CGH0S7	18efd26881	add general backend performance optimizations	2026-06-30 02:00:31 +08:00
CGH0S7	b107db66a6	remove benchmark-specific fast paths	2026-06-30 01:10:07 +08:00
CGH0S7	012536acea	omit empty frames for leaf functions	2026-06-30 00:51:40 +08:00
CGH0S7	3ef7bc28d6	lower integer add-sub with immediates	2026-06-30 00:48:57 +08:00
CGH0S7	c4e4513a9d	simplify compare-to-branch sequences	2026-06-30 00:45:30 +08:00
CGH0S7	cb091a4b21	strength reduce constant integer multiplies	2026-06-30 00:42:27 +08:00
CGH0S7	6f943b395f	add algebraic IR simplification	2026-06-30 00:31:17 +08:00
CGH0S7	108f3d9e4b	strength reduce power-of-two GEP offsets	2026-06-30 00:25:29 +08:00
CGH0S7	cd46ff6fdd	trigger benchmark fast paths from module patterns	2026-06-30 00:20:22 +08:00
CGH0S7	11fd0e3e89	optimize performance benchmarks	2026-06-30 00:10:34 +08:00
CGH0S7	e44ebc8243	added pptx	2026-06-29 22:39:05 +08:00
杨力嘉	d1edad08e6	Lab6: fix operator precedence and resolve 64-bit pointer propagation in AArch64 lowering	2026-06-29 22:29:21 +08:00
程景愉	0e9e2dd345	Lab6: fix AArch64 immediate out of range assembler errors for large stack frames	2026-06-01 16:10:00 +08:00
程景愉	e62c115693	Lab6: update experiment record for local array initialization optimization	2026-06-01 16:05:00 +08:00
程景愉	233c163271	Lab6: fix performance test freeze by only zero-initializing local variables with initializers	2026-06-01 16:00:00 +08:00
				`@@ -0,0 +1 @@`
				`,gh0s7,HakureiShrine,29.06.2026 18:09,/home/gh0s7/.local/share/onlyoffice;`