4 Commits

Author	SHA1	Message	Date
舒钰权	4475e91bd8	Lab5: Implement register-aliasing-aware peephole optimization pass for redundant stack instruction elimination	2026-05-18 14:30:22 +08:00
程景愉	0b0bc04be3	feat: complete Lab3 instruction selection and assembly generation	2026-04-25 14:30:22 +08:00
Lane0218	b1155d8fa9	refactor(dev): 统一 IR/MIR 接口命名风格	2026-03-12 15:17:02 +08:00
Lane0218	b939fc40ee	feat(mir): 增加 Lab3 AArch64 MVP 后端与 --emit-asm 支持	2026-03-07 22:41:53 +08:00