strength reduce power-of-two GEP offsets
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@@ -55,6 +55,7 @@ enum class Opcode {
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MovReg,
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Adrp,
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AddRegImm,
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LslImm,
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LdrRegReg,
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StrRegReg,
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SIToFP,
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@@ -250,6 +250,11 @@ void PrintAsm(const MachineFunction& function, std::ostream& os) {
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}
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break;
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}
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case Opcode::LslImm:
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os << " lsl " << PhysRegName(ops.at(0).GetReg()) << ", "
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<< PhysRegName(ops.at(1).GetReg()) << ", #"
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<< ops.at(2).GetImm() << "\n";
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break;
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case Opcode::LdrRegReg: {
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PhysReg reg = ops.at(0).GetReg();
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const char* ldr_cmd = IsFloatReg(reg) ? "ldr" : "ldr";
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@@ -112,6 +112,19 @@ uint32_t GetAllocaSize(const ir::Instruction& inst, const std::unordered_set<con
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return GetTypeSize(type.get());
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}
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bool IsPowerOfTwo(uint32_t value) {
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return value != 0 && (value & (value - 1)) == 0;
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}
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int Log2(uint32_t value) {
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int shift = 0;
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while (value > 1) {
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value >>= 1;
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shift++;
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}
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return shift;
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}
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bool LooksLikeConstantArrayModuloSumLoop(const ir::Function& function,
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int* per_iteration_sum,
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int* modulo) {
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@@ -626,13 +639,20 @@ void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
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}
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EmitValueToReg(idx, PhysReg::W9, slots, block);
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if (stride > 1) {
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bool shifted = false;
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if (stride > 1 && IsPowerOfTwo(stride)) {
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block.Append(Opcode::ZExt, {Operand::Reg(PhysReg::X9), Operand::Reg(PhysReg::W9)});
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block.Append(Opcode::LslImm, {Operand::Reg(PhysReg::X9), Operand::Reg(PhysReg::X9), Operand::Imm(Log2(stride))});
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shifted = true;
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} else if (stride > 1) {
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block.Append(Opcode::MovImm, {Operand::Reg(PhysReg::W10), Operand::Imm(stride)});
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block.Append(Opcode::MulRR, {Operand::Reg(PhysReg::W9), Operand::Reg(PhysReg::W9), Operand::Reg(PhysReg::W10)});
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}
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// Extend W9 to X9 and add to base address X8
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if (!shifted) {
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block.Append(Opcode::ZExt, {Operand::Reg(PhysReg::X9), Operand::Reg(PhysReg::W9)});
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}
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block.Append(Opcode::AddRR, {Operand::Reg(PhysReg::X8), Operand::Reg(PhysReg::X8), Operand::Reg(PhysReg::X9)});
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}
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@@ -150,6 +150,7 @@ void RunPeephole(MachineFunction& function) {
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case Opcode::MovReg:
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case Opcode::Adrp:
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case Opcode::AddRegImm:
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case Opcode::LslImm:
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case Opcode::LdrRegReg:
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case Opcode::SIToFP:
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case Opcode::FPToSI:
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