Support 2nd and 8th order CUDA AMR paths
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@@ -245,11 +245,15 @@ bool cuda_cell_gw3_restrict_params(const Parallel::gridseg *src,
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const Parallel::gridseg *dst,
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int first_fine[3])
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{
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#if (USE_CUDA_BSSN || (USE_CUDA_Z4C && (ABEtype == 2))) && defined(Cell) && ((ghost_width == 3) || (ghost_width == 4))
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#if ghost_width == 4
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#if (USE_CUDA_BSSN || (USE_CUDA_Z4C && (ABEtype == 2))) && defined(Cell) && (ghost_width >= 2) && (ghost_width <= 5)
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#if ghost_width == 5
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const int stencil_hi = 5;
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#elif ghost_width == 4
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const int stencil_hi = 4;
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#else
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#elif ghost_width == 3
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const int stencil_hi = 3;
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#else
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const int stencil_hi = 2;
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#endif
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if (!src || !dst || !src->Bg || !dst->Bg)
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return false;
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@@ -291,11 +295,15 @@ bool cuda_cell_gw3_prolong_params(const Parallel::gridseg *src,
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int first_fine_ii[3],
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int coarse_lb[3])
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{
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#if (USE_CUDA_BSSN || (USE_CUDA_Z4C && (ABEtype == 2))) && defined(Cell) && ((ghost_width == 3) || (ghost_width == 4))
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#if ghost_width == 4
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#if (USE_CUDA_BSSN || (USE_CUDA_Z4C && (ABEtype == 2))) && defined(Cell) && (ghost_width >= 2) && (ghost_width <= 5)
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#if ghost_width == 5
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const int stencil_hi = 5;
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#elif ghost_width == 4
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const int stencil_hi = 4;
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#else
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#elif ghost_width == 3
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const int stencil_hi = 3;
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#else
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const int stencil_hi = 2;
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#endif
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if (!src || !dst || !src->Bg || !dst->Bg)
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return false;
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